13.1 CORE Generator - Generating a core through Project Navigator causes VHDL example files to be overwritten

AR#	32396	Search For Another Answer
Topic	CORE Generator
Last Updated	12/21/2011
Status	Active

Description

If an IP core is created in or regenerated through Project Navigator, the functional model and other supporting HDL files are generated for both HDL languages. For IP cores which generate an example design, some of the file names are the same in the "simulation" folder regardless of the language generated, so files are overwritten and do not work if it is not for the first language generated.

This issue affects MIG, Endpoint Block for PCI Express Core, Serial Rapid I/O, and some networking cores which generate an example design.

Solution

Writing out source files for both Verilog and VHDL is expected behavior. However, for this set of IP cores, this behavior interferes with the simulation scripts for the example designs.

To work around this issue, open the CORE Generator tool outside of Project Navigator and regenerate the core with the preferred language selected in the project properties.

This issue has been resolved in ISE Design Suite 13.2.