AR# 32398 11.1 EDK, xps_timer_v1_00_a - Registers are not initialized to '0' after core reset

Description
Solution

Keywords: Load registers, Load_Counter_Reg, Write_Load_Reg

The following registers, Load registers, Load_Counter_Reg, Write_Load_Reg and others, are not set to '0' in the hardware after core reset. This is not according to the data sheet.

This issue has been fixed in the latest release of the xps_timer_v1_01_a core and is available in EDK 11.1.

The EDK 11.1 will be available at:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp

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AR# 32398
Date Created	04/09/2009
Last Updated	04/21/2009
Status	Active
Type

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AR# 32398 11.1 EDK, xps_timer_v1_00_a - Registers are not initialized to '0' after core reset

Description

Solution

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