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AR# 3243

M1.4 Map - Timespec'ing RAMS (dualport) to FFS only covers SPO path.


When using the TIMEGRP constraint in a UCF to constrain the paths between the dual port RAMs and connected flops, only the F LUTs get referenced in the PCF. This only covers the SPO (associated with the FLUT) but not the DPO (associated with G LUT).

Notice the first TIMEGRP line contains only BEL "ram16d_spo", repeated
twice. The BEL's name "ram16d_spo" is based on the output SPO net. The
DPO net has the name "ram16d_dpo", so the TIMEGRP line was changed
like so:

TIMEGRP "RAMS(ram16d*)" = BEL "ram16d_spo" BEL "ram16d_dpo" BEL "ram16d_spo" ;

This works. TRCE now controls both SPO and DPO.

(Oddly PERIOD constraint will cover this.)


This issued has been fixed in the mapper so that the correct .pcf
constraints are written. This fix is included in the current M1.4 Core
Applications patch available from the Xilinx Download Area:

Solaris: http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/core_sol17_m14.tar.Z
SunOS http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/core_sun17_m14.tar.Z
HPUX: http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/core_hp17_m14.tar.Z
Win95/NT: http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/core_nt17.zip

AR# 3243
Date Created 12/24/1997
Last Updated 03/27/2000
Status Archive
Type General Article