UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 3245

M1.4 Map - Mapper unable to merge a RAM and Flop with opposite clock polarities

Description

ERROR:x4kma:312 - The following symbols could not be constrained
to a single CLB: RAM16X1S symbol "HREG_1/BANK2/DELTA/RAM1" (output
signal=HREG_1/BANK2/DELTA/D0) FDCE symbol "HREG_1/BANK2/DELTA/FF1"
(output signal=HREG_1/OUT2D0) The clock signals are of opposite polarity. These symbols share the same RLOC attribute value, which requires them
to be mapped to the same CLB.

Solution

A fix for this merge problem is included in the current M1.4 Core
Applications patch available from the Xilinx Download Area:

Solaris: http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/core_sol17_m14.tar.Z
SunOS http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/core_sun17_m14.tar.Z
HPUX: http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/core_hp17_m14.tar.Z
Win95/NT: http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/core_nt17.zip
AR# 3245
Date Created 12/24/1997
Last Updated 04/03/2000
Status Archive
Type General Article