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AR# 32461

11.4 Timing Known Issue - There are setup violations, but the paths are not reported

Description

PAR reports that there are timing violations. TheTRACE reports violations under constraints, but I do not see the actual paths listed with the violations. How can I report these failing paths? 

Following is an example: 

========================================

Timing constraint: TS_RDClk_P = PERIOD TIMEGRP "RDClk_P" 400 MHz HIGH 50% 
INPUT_JITTER 0.3 ns; 

34 paths analyzed, 34 endpoints analyzed, 11 failing endpoints 
11 timing errors detected. (11 setup errors, 0 hold errors, 0 component switching limit errors) 
Minimum period is 1.666ns. 

------------------------------------------------------------------------ 

========================================

Timing constraint: TS_SnkCalFlops = MAXDELAY FROM TIMEGRP "snk_cal_flops" TO 
TIMEGRP "snk_cal_flops" TS_RDClk_P / 4; 
1070 paths analyzed, 518 endpoints analyzed, 0 failing endpoints 
0 timing errors detected. (0 setup errors, 0 hold errors) 
Maximum delay is 3.461ns. 

------------------------------------------------------------------------ 

========================================

Solution

This is a known issue that Xilinx is currently investigating. 

A solution is scheduled for the next major release.

AR# 32461
Date Created 04/10/2009
Last Updated 05/23/2014
Status Archive
Type Known Issues
Tools
  • ISE - 10.1
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • More
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
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