11.1 Virtex-5 MAP Known Issues - Incorrect optimization of latch with Gate driven by constant "1" but GE driven by active signal
Description
I have a latch in my design with G constantly high and an active signal on D. It has been optimized away so as to pass through the D signal despite the fact that GE is active. Is this optimization problem a known issue?
Solution
This latch optimization issue is scheduled to be fixed in ISE 11.2.
Applies To
Devices
- Virtex-5 FXT
- Virtex-5 LX
- Virtex-5 LXT
- Virtex-5 SXT
- Virtex-5 TXT
- Virtex-5Q
- Virtex-5QV
Design Tools
- ISE Design Suite - 11.1