My Spartan-3E/A design is crashing during the Phase 4.2. What is this phase and is this a known problem?
Phase 4.2 is the clock placement phase where the location of clock components is determined or, in the case of locked components, validated. There is a known problem in ISE 11.1 where when a certain error condition is detected, the error handling code causes a crash. This error condition should trigger the following error message:
ERROR:Place:1264 - A conflict between the loads of two BUFGs has been found.
There is a restriction that no pair of BUFGs can drive loads in the same
quadrant of the device.
This error occurs when there is a conflict between an All-Quadrant BUFG and its paired Side BUFG which can not drive loads in the same clock region due to shared routing resources. For more information on this restriction see (Xilinx Answer 19947).
This problem will be fixed in ISE 11.2. Meanwhile, examine the BUFG locations chosen for the conflicts mentioned above.