Keywords: Virtex-5 FXT, clock correction, RXDATA, RXCLKCORCNT, error
Xilinx has determined that the Clock Correction feature of the Virtex-5 GTX transceiver can cause data corruption on the Receiver when a clock correction sequence is skipped or added. The XAUI core is effected by this issue because it must use a clock correction sequence length of 1 byte to adhere to the IEEE 802.3 standard.