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AR# 32614

Serial RapidIO - PHY does not pass CRF bit correctly on RX frames


Known Issue: v5.2, v5.1.1, v5.1, v4.4.2, v4.4.1, v4.4, v4.3, v4.2, v4.1

Packets received by the SRIO PHY and Logical layer with the CRF bit set in the packet header are passed to the user from the Logical layer without CRF signaling (e.g., "mreq_crf" asserted). The issue originates from the PHY layer, where the PHY is not asserting the "crf_bit_rx" signal for the entire length of the received packet, as described in the core's User Guide (UG503). Since the Buffer design checks the crf_bit_rx signal only on the SOF, the CRF flag is not passed up to the Logical layer.


This issue is scheduled to be fixed in the ISE 11.3 release. A work-around is available for the SRIO v4.x cores, but not the v5.x cores.

The PHY core will always assert crf_bit_rx on the EOF at a minimum, so the work-around is to have the buffer detect crf_bit_rx on the EOF instead of SOF and pass this through to the Logical layer.

If you encounter this problem, please open a WebCase with Xilinx Technical Support for further assistance:


Revision History

04/29/2009 - Initial Release

AR# 32614
Date Created 04/29/2009
Last Updated 12/15/2012
Status Active
Type General Article