We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 32632

SPI-4.2 v9.1- "ERROR:Place:909 - Regional Clock Net "core_pl4_src_top0/tsclk_gp" cannot possibly be routed..." message during MAP for Source core


The SPI-4.2 Source core in some cases might fail MAP with the following error:

"ERROR:Place:909 - Regional Clock Net "core_pl4_src_top0/tsclk_gp" cannot possibly be routed to component "core_pl4_src_top0/U0/cal0/TStat_d1<0>" (placed in clock region "CLOCKREGIONP_X1Y4"), since it is too far away from source BUFR "core_pl4_src_top0/U0/clk0/tsbr" (placed in clock region "CLOCKREGION_X1Y0")."


This is a MAP tool issue where MAP is not able to place a TStat* pin in a bank that can be reached by the BUFR clock.

One possible work-around is to manually place the BUFR component to an appropriate location relative to the TStat pins.

Alternatively, the TStat* pins can be manually placed in a bank reachable by the BUFR being used by the tools. This can be added as a constraint to the UCF.

For example:
INST "TStat*" LOC = "Bank14";

This issue is fixed in 11.3

Revision History
05/04/2009 - Initial Release
04/07/2010 - Added fixed version

AR# 32632
Date Created 05/04/2009
Last Updated 04/07/2010
Status Active
Type General Article