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AR# 32634

ISE Design Suite 11 DSP Tools (System Generator for DSP and AccelDSP Synthesis Tool) Update 2 (11.2) - README


Keywords: MATLAB, Simulink, errata, KI, SysGen, 11.2

This Answer Record contains the Release Notes and Known Issues for System Generator for DSP 11.2.


For System Generator for DSP Release Notes from other versions, see (Xilinx Answer 29595).

This README Answer Record contains installation instructions and a list of the issues that are fixed in the System Generator for DSP 11.2 Update. A successful installation of ISE Design Suite 11.2 changes your software version number to 11.2. (Verify by running xlVersion at the MATLAB prompt.)

Installation Instructions

1. Download "Xilinx_11.2_ISE_DS_<platform>.tar" from http://license.xilinx.com/getLicense?group=esd_oms&tab=DownloadUpdates
2. Untar the archive. For more information about tar files, see (Xilinx Answer 32818).
3. Open the untarred archive and run "xsetup(.exe)".
4. Select the root location of ISE Design Suite as your destination directory (that is, C:\Xilinx\11.1 or /opt/Xilinx/11.1).

NOTE: XilinxUpdate run from your ISE Design Suite can also be used to download and install updates. Please see the Help System for more information on running XilinxUpdate.

For more information on what other products are included in this update, please see (Xilinx Answer 33216).

Release Notes and Known Issues in System Generator for DSP 11.2

Please read the documentation, because it answers questions you might have about changes to the functionality or the look from previous versions of System Generator for DSP. The System Generator User Guide is accessible in PDF format at:

11.2 System Generator Enhancements
To see a list and description of the new features in 11.2, see the System Generator User Guide:

Product Change Notice
Starting with this release, further development of the AccelDSP synthesis tool has been discontinued. You may continue to use this version of the tool with ISE Design Suite 11. The tool will not be included in ISE Design Suite 12.


- Why does the design fail to generate when using an IP core? Why do I receive "Error 0001: caught standard exception" during generation? See (Xilinx Answer 23614).

Installation and setup
- What software is required to install System Generator for DSP? See (Xilinx Answer 17966).
- How can I tell if the DSP Tools are installed and configured for use in MATLAB? See (Xilinx Answer 32257).
- How can I switch between multiple versions of System Generator for one MATLAB installation? See (Xilinx Answer 24842).
- How can I install just the DSP Tools without reinstalling all of the IDS tools? See (Xilinx Answer 32258).
- Which version of System Generator supports the latest version of MATLAB? See (Xilinx Answer 25306).
- Why do I receive "Error while executing C MEX S-function 'sysgen', (mdlTerminate). Unexpected unknown exception from MEX file" when I simulate my System Generator model? How do I set up my system environment properly? See (Xilinx Answer 31095).
- When using System Generator on Windows Vista, why do I receive the error: "gcc.exe: installation problem, cannot exec `cc1': No such file or directory. Error occurred during "Simulation Initialization"? See (Xilinx Answer 30977).
- When using System Generator on a 64-bit XP machine, why do I receive a message stating, "There is a problem with your Xilinx ISE installation or with your Xilinx environment variable" and "could not run java.exe"? See (Xilinx Answer 29512).

MATLAB and Simulink interaction
- Why do I receive an error message stating "continuous sample times are not allowed" when driving a Simulink Spectrum Scope with Xilinx System Generator blocks? See (Xilinx Answer 31933)
- Why is the sample rate passed to Simulink blocks from my gateway out different than the sample rate passed to my System Generator blocks? See (Xilinx Answer 30131).
- Why do I receive a "xlSimulationRequired" or "Reference to a cleared variable sysgen_return_status" error when I try to generate the design? See (Xilinx Answer 21750).
- An indeterminate input data (also known as a NAN) error occurs when design is simulated. See (Xilinx Answer 23000).
- Why am I unable to access the quantization parameters in the FDATool in System Generator? See (Xilinx Answer 24616).
- Why do I receive a Simulink message stating, "Use of this data type requires a fixed-point license, but license checkout failed"? See (Xilinx Answer 25255).
- What is the recommended Simulink simulation solver? Why do I see incorrect behavior when a fixed-step solver is used? See (Xilinx Answer 23328).
- Why doesn't my data appear downsampled when I use "first value of frame" with a latency of 0 with the downsample block? See (Xilinx Answer 32810).
- Why do I receive an internal error or see MATLAB crash if I use the Simulink Simulation option "Accelerator"? See (Xilinx Answer 32856).

Third-Party Synthesis Tools
- I cannot generate an NGC, Bitstream, Timing Analysis, or Hardware in the Loop target when using Synplify as my synthesis tool. Why? See (Xilinx Answer 24273).
- Why do I receive the message "Failed to execute command "project set {Synthesis Tool} {Synplify Pro (VHDL/Verilog)}"" when trying to use Synplify Pro for my synthesis tool from System Generator? See (Xilinx Answer 31112).
- Why are there simulation mismatches at the beginning of the HDL simulation generated from System Generator for DSP when Synplify is used for synthesis? See (Xilinx Answer 29170).

- Why do I see an instantiated register called "xlpersistentdff" in a System Generator for DSP design? See (Xilinx Answer 24257).
- JTAG Hardware Co-Sim with non-Xilinx parts in the chain causes error. See (Xilinx Answer 19599).
- Why do I receive a standard exception error message when I generate my model? See (Xilinx Answer 29430).

Known Issues

- When I use the CIC Compiler filter with an input data rate less than the system clock rate controlled by ND, I see mismatches between the simulation results in System Generator versus hardware co-simulation. See (Xilinx Answer 31455).
- When running a MATLAB Student Edition, why do I receive the error message "Error evaluating 'OpenFcn' callback of Xilinx Gateway In Block block (mask)"? See (Xilinx Answer 31934).
- Why do I receive "Fatal Internal Error" when my design contains "inport" and "output" blocks at the top level of my Simulink model for Data Import/Export? See (Xilinx Answer 31935).
- Why do I see mismatches in HDL simulation with the System Generator generated testbench when my design contains the DDS Compiler block using either the frequency synthesis or SIN/COS Lookup Table? See (Xilinx Answer 32121).
- Why am I unable to search the System Generator documentation and copy text from it when using MATLAB R2008a? See (Xilinx Answer 32172).
- I do not obtain an m-code based hardware co-sim stimulus file when I generate my hardware co-sim token. Why? See (Xilinx Answer 33117).
- Why does the Multiplier block use fabric when I specified "use embedded multipliers"? See (Xilinx Answer 33122).
- Why do I receive NGDBuild errors regarding illegal buffers when I generate my EDK Processor design to a Hardware co-simulation target? See (Xilinx Answer 33125).
- The CE_CLR pin is not available on my generated netlist when I check "Provide clock enable clear pin". Why? See (Xilinx Answer 33163).

Linux Only
- Can I perform Ethernet-based hardware co-simulation on a Linux machine? See (Xilinx Answer 32221).
- Why is the System Generator blockset empty when I try to open it in Simulink when running on Linux? See (Xilinx Answer 32173).
- Why do I receive an error when I target the "Timing Analysis" flow on Linux? See (Xilinx Answer 32991).
- When I click the System Generator help link from the MATLAB help in Linux, the link is broken. See (Xilinx Answer 32995).
- Why do I receive an error message that an Unsupported version of ISE is found even though I have ISE 11 installed? See (Xilinx Answer 33059).

AR# 32634
Date Created 06/10/2009
Last Updated 07/29/2009
Status Active
Type General Article