Solution

Known Issues
(Xilinx Answer 32477) 11.1 PlanAhead - Incorrect syntax written to Timespec PERIOD using predefined groups
(Xilinx Answer 32464) 11.1 PlanAhead - When I create a new timing constraint, the NET PERIOD is chosen in the Wizard
(Xilinx Answer 32463) 11.1 PlanAhead - Does PlanAhead have to run XDL every time I run Implementation?
(Xilinx Answer 32380) 11.1 PlanAhead - How do I modify options for an Implementation Run that has been completed?
(Xilinx Answer 32383) 11.1 Timing Analyzer, PlanAhead Release Note - Timing parameter link opens data sheet, but "No matches were found."
(Xilinx Answer 32478) 11.1 PlanAhead - Ports assigned to multiple locations do not cause errors
(Xilinx Answer 32462) 11.1 PlanAhead - Removed sources remain in PlanAhead project
(Xilinx Answer 32476) 11.1 PlanAhead - Creating Basic Group constraint only allows 1 instance to be specified
(Xilinx Answer 32399) 11.1 PlanAhead - Are non-English Characters supported in PlanAhead Project Names?
(Xilinx Answer 32481) 11.1 PlanAhead - Does PlanAhead support the IODELAY_GROUP constraint?
(Xilinx Answer 32472) 11.1 PlanAhead - Importing a UCF with pblocks leads to duplicate pblocks
(Xilinx Answer 32777) 11.1 PlanAhead - Unable to run Tutorials with WebPACK installation
(Xilinx Answer 33367) 11.3 PlanAhead - DRC is allowing signals connected to IBUFGDS to be placed at non-clock pins
(Xilinx Answer 33152) PlanAhead 11.2 - DRC errors on clock placement for Spartan-3 derivatives
(Xilinx Answer 33327) 11.2 PlanAhead - My Pblock statistics do not match the utilization in the metrics for the same Pblock. Why?
(Xilinx Answer 33800) 11.4 PlanAhead - Elaboration fails with std_logic_vector(0:0).
(Xilinx Answer 33801) 11.4 PlanAhead - Can I change the width of my I/O Buses in Initial Pin Planning mode?

11.2 Resolved Issues
(Xilinx Answer 31716) 10.1 PlanAhead - DRC Error "I/Os placed on prohibited sites" on pin AC5 in Virtex-5 with FF1136 package
(Xilinx Answer 31852) PlanAhead 10.1 - One or more Vr sites in bank I/O Bank occupied.
(Xilinx Answer 32482) 11.1 PlanAhead - Does PlanAhead DRC report single-ended clocks on the N side of a differential pair?
(Xilinx Answer 32466) 11.1 PlanAhead - How do I assign a port to a non-ideal pin?
(Xilinx Answer 32479) 11.1 PlanAhead - A Spartan-3E GCLK placement is unnecessarily inflexible
(Xilinx Answer 32471) 11.1 PlanAhead - False IDLYCTRL0 Error on Virtex-5 floorplans
(Xilinx Answer 32468) 11.1 PlanAhead - "ERROR: [HD-DB 2]Part: xc4vlx100ff1148-10 has no WASSO data for IOStd LVDS_25"

11.3 Resolved Issues
(Xilinx Answer 33326) 11.1 PlanAhead/Project Navigator - Why are all UCFs in an ISE project updated when I modify one in the PlanAhead tool?

11.4 Resolved Issues
(Xilinx Answer 33367) 11.3 PlanAhead - DRC is allowing signals connected to IBUFGDS to be placed at non-clock pins
(Xilinx Answer 33522) 11.3 Spartan-6 FPGA PlanAhead tool - I cannot constrain my differential inputs in banks 1 and 3 for Spartan-6 devices
(Xilinx Answer 33366) 11.3 PlanAhead - When I close and reopen a floorplan, all user defined columns and their contents in the Package Pins window are gone
(Xilinx Answer 33452) 11.3 PlanAhead - PlanAhead install pointed to with UNC path crashes when opening project.


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This README Answer Record contains installation instructions and a list of the issues that are fixed in PlanAhead 11.2 Updates. A successful installation of PlanAhead 11.2 Update changes your software version number to 11.2

The destination directory specified during the setup operation must contain an existing Xilinx ISE installation. Any new device support not previously installed should first be installed before adding the Update.


Installation Instructions for Windows Users


1. Download "Xilinx_11.2_ISE_DS_win(64).tar" from http://license.xilinx.com/getLicense?group=esd_oms&tab=DownloadUpdates

2. Untar the archive. For more information about tar files see (Xilinx Answer 32818).

3. Open the untarred archive and run "xsetup.exe" by double-clicking on it.

4. Select the root location of ISE Design Suite as your destination directory (i.e., C:\Xilinx\11.1).



Installation Instructions for Linux Users


1. Download "Xilinx_11.2_ISE_DS_lin(64).tar" from http://license.xilinx.com/getLicense?group=esd_oms&tab=DownloadUpdates

2. Untar the archive. For more information about tar files see (Xilinx Answer 32818).

3. Open the untarred archive and run "xsetup" by typing ./xsetup to a terminal.

4. Select the root location of ISE Design Suite as your destination directory.


NOTE: Web XilinxUpdate can also be used to download and install ISE Updates by typing xilinxupdate into a terminal/command prompt or through ISE -> Help -> XilinxUpdate.


For more information on what other products are included in this update, please see (Xilinx Answer 33216)