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AR# 32641

MIG v3.1 - Release Notes and Known Issues for ISE Design Suite 11.2


This Release Notes and Known Issues Answer Record is for the Memory Interface Generator (MIG) v3.1 released in ISE Design Suite 11.2 and contains the following information:  


- General Information  

- Software Requirements 

- New Features  

- Resolved Issues 

- Known Issues  


For installation instructions, general CORE Generator interface known issues, and design tools requirements, see the IP Release Notes Guide at: 



General Information  

MIG v3.1 is available through ISE Design Suite 11.2.  


For a list of supported memory interfaces and frequencies for Spartan-3 FPGA Generation, Virtex-4 and Virtex-5 FPGAs, see the MIG User Guide: 


For a list of supported memory interfaces and frequencies for the Spartan-6 FPGA MCB, see the Spartan-6 FPGA Memory Controller User Guide: 


For a list of supported memory interfaces and frequencies for Virtex-6 devices, see the Virtex-6 FPGA Memory Interface Solutions User Guide: 



Software Requirements 

- Xilinx ISE Design Suite 11.2 

- Synplify Pro C-2009.03 support 

- 32-bit Windows XP 

- 32-bit Linux Red Hat Enterprise 4.0 

- 64-bit/32-bit Linux Red Hat Enterprise 4.0 

- 64-bit XP professional 

- 32-bit Vista business 

- 64-bit SUSE 10 

- 64-bit/32-bit Linux Red Hat Enterprise 5.0 support 

- 64-bit Windows Vista support 

- 32-bit SUSE 10 support 



New Features 

- ISE Design Suite 11.2 software support 

- Virtex-6 FPGA support 

- Spartan-6 FPGA support 

- DDR2 SDRAM 4 GB memory part support for Virtex-4 and Virtex-5 FPGA designs 



Resolved Issues 

DDR2 SDRAM Virtex-5 FPGA  

- Added a default condition to case statement in phy_calib.v module to resolve simulation warnings. 

- CR 451140 

- Replaced IDDR with FDCPE to resolve BITGEN dangling pin warnings. 

- CR 508721 

- VHDL external simulation testbench (sim_tb_top.vhd) properly sets frequencies for all interfaces in multi-controller designs. 

- CR 513310 





- (Xilinx Answer 32375) MIG 2.3, 3.0, Virtex-5 FPGA QDRII - Potential for small margin between the CQ and FPGA clock after stage 2 calibration for frequencies between 125 - 250 MHz 

- CR 517643 

- (Xilinx Answer 31579) MIG v2.3, v3.0 - Virtex-5 FPGA QDRII: ERROR:Place:899 - The following IOBs use DCI and have been locked to the I/O bank # 

- (Xilinx Answer 32318) MIG v3.0, Virtex-5 FPGA QDRII - Design does not complete calibration in hardware when using Synplify Pro 9.6.2 as the synthesis tool 

- VHDL external simulation testbench (sim_tb_top.vhd) properly sets frequencies for all interfaces in multi-controller designs. 

- CR 513310 




DDR2 SDRAM Virtex-4 FPGA Direct Clocking 


DDR2 SDRAM Virtex-4 FPGA Serdes Clocking  

- Attribute syn_preserve is replaced with syn_noprune for Synplicity design. 

- CR 514149 

- Improvements made to pin algorithm for Data Group selection in center banks. 

- CR 513309 









- Improved pin-out algorithm to properly place rst_dqs_div_in/_out in the center of the data bits for all configurations. 

- CR 519854 

- CR 519113 

- CR 518533 

- Improved pin-out algorithm to select more efficient pin-outs when compatible devices are selected. 

- CR 519112 

- Output proper I/O standard constraints in UCF when compatible parts are selected. 

- CR 511975 


Updates to Virtex-5, Virtex-4, and Spartan-3 FPGA Generation MIG User Guide (ug086) 

- Added more details on the parameters that Verify UCF/Update Design verifies. 

- CR 518202 

- CR 518200 

- Added complete Spartan-3 FPGA Generation pin allocation rules. 

- CR 517690  

- Corrected support tables for DDR SDRAM SODIMM packages. 

- CR 517285  

- Updated Chapter 1 with proper screen shots and corrected the description text and information in tables. 

- CR 510253  

- Deleted the DDR2 SDRAM reference for Spartan-3E FPGA family as DDR2 SDRAM is not supported for Spartan-3E FPGA.  

- CR 518759  

- Added notes about Virtex-4 FPGA DDR2 SDRAM simulation warnings due to rounding of the clock period.  

- CR 481582  

- Added notes about Virtex-4 FPGA DDR2 SDRAM deep design simulation warnings.  

- CR 498876  

- Added DDRII SRAM memory implementation guidelines to appendix. 

- CR 517642  


MIG Tool  

- (Xilinx Answer 32615) MIG v3.0 - Get "ERROR:TclTasksC:project_095: Unknown property" when running create_ise.bat  

- CR 513311 - Create.ise script uses correct ISE design tools 11.1 options 

- (Xilinx Answer 32475) MIG v3.0, Spartan-3 FPGA Generation DDR/DDR2 - Known issues with Verify UCF and Update Design 

- CR 517689 - Verify UCF properly errors when the rst_dqs_div_in/_out signals are not allocated in the center of the DQ bits. 

- CR 517538, 517537 - Verify UCF and Update Design function properly with an input UCF that only contains IO LOC constraints. 

- (Xilinx Answer 32319) MIG v3.0 - A ".ise" project is not successfully created after I run the create_ise.bat file 

- CR 513311 

- (Xilinx Answer 31579) MIG v2.3, v3.0 Virtex-5 QDRII - "ERROR:Place:899 - The following IOBs use DCI and have been locked to the I/O bank #" 

- CR 481353 

- Memory density value is reflected properly in the Memory Details for DIMMs created using Create Custom Part. 

- CR 517905 

- For all Virtex-5 FPGA designs, the output write timing spreadsheets properly list the duty cycle distortion parameter in reference to a PLL. 

- CR 517904 

- MIG will flag a warning message and it will no longer crash if it does not find the Custom memory part.  

- CR 510496 

- Fixed DCI selection issue for QDRII and DDR2 SDRAM multi-controller designs.  

- CR 510216 

- Corrected License Agreement page issues for Virtex-4 FPGA QDRII and DDRII SRAM designs. 

- CR 510215 

- Added notes to the Bank Selection page as to why bank 3 and bank 4 cannot be used for data, address and control signals. 

- CR 470630 

- Resolved special characters display issue in Japanese OS. 

- CR 510723 

- Implementation script files, ise_flow.bat, updated to first delete implementation files from previous build. 

- CR 513260 

- MIG sets the executable permissions to all the batch files in Linux.  

- CR 513869 

- Verify UCF properly verifies the frequency in the mig.prj is supported for the FPGA speed grade. 

- CR 517984 

- Created clear error messages for Verify UCF and Update Design when Spartan-3 FPGA Generation DQ IO placement violates p/n rules. 

- CR 514741 

- GUI issues resolved when targeting Virtex-5 FPGA Multi-Controller designs with 8 controllers 

- CR 510975 



Known Issues  

- Virtex-6 and Spartan-6 FPGA solutions are pending hardware validation. 


(Xilinx Answer 32829) MIG v3.1 - Virtex-6 FPGA Low Power Devices not yet supported.  

(Xilinx Answer 32830) MIG v3.1, Virtex-6 FPGA DDR2 - Master Bank must be selected in GUI even when default banks are used.  

(Xilinx Answer 32839) MIG v3.1, Virtex-6 FPGA DDR2/DDR3 - Non-zero values for Additive Latency are not supported  

(Xilinx Answer 32868) MIG v3.1, Virtex-6 FPGA: Enabling KEEP_HIERARCHY option in synthesis causes ERROR:PhysDesignRules:368 during BitGen  

(Xilinx Answer 32872) MIG v3.1, Virtex-6 FPGA - # ** Error: (vsim-8604) NaN results from division operation  

(Xilinx Answer 32873) MIG v3.1, Virtex-6 FPGA DDR2/DDR3 - False memory model violations might occur in simulation  

(Xilinx Answer 32874) MIG v3.1, Virtex-6 FPGA DDR3 - MIG lists support for the MT9JSF12872XX-1G1, which could represent two different Micron devices  

(Xilinx Answer 32930) MIG v3.1, Virtex-6 FPGA DDR3 - Changes required to simulation testbench (sim_tb_top.v) to skip calibration and avoid memory overflow errors 


(Xilinx Answer 32869) MIG v3.1, Spartan-6 FPGA MCB - When a MIG MCB project is reloaded using Recustomize (Under Original Settings) display issues occur 

(Xilinx Answer 32924) MIG v3.1, Spartan-6 FPGA MCB - When controllers C1, C2, and C4 are selected, C4 can only be selected as DDR2 SDRAM. 

(Xilinx Answer 33356) Spartan-6 FPGA MCB - X4 memory components are not supported until IDS 11.4 (MIG 3.3)  

(Xilinx Answer 33357) Spartan-6 FPGA MCB - Port 3 is not supported in read mode when all 6 ports are configured 

(Xilinx Answer 33358) Spartan-6 FPGA MCB: ERROR:Place:864 errors occur during PAR when data mask is disabled  


(Xilinx Answer 32870) MIG v3.1, Virtex-6 FPGA QDRII+ SRAM - MIG does not properly restrict Data Read group bank selection which could result in "ERROR: Place:906" during MAP 

(Xilinx Answer 32925) MIG v3.1, Virtex-6 FPGA QDRII+ - Issues exist in calibration logic that require an updated phy_read_stage1_cal.v module 

(Xilinx Answer 33289) MIG v3.1, Virtex-6 FPGA QDRII+ - Changes required to Samsung simulation model for proper operation and completion of calibration 


(Xilinx Answer 32871) MIG v3.1, Virtex-5 FPGA DDR2 SDRAM - TWR violations occur at low frequencies  

(Xilinx Answer 32610) MIG 3.1, Virtex-5 FPGA DDR2: TWTR violations may occur at low frequencies in simulation and hardware (Xilinx Answer 32919) MIG v3.1, Virtex-5 FPGA - Verilog designs using Synplify Pro C-2009.03 will fail in MAP with "ERROR:MapLib:1114"

AR# 32641
Date Created 06/11/2009
Last Updated 09/23/2014
Status Active
Type General Article
  • ISE Design Suite - 11.2
  • MIG