UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 32645

CPRI v2.1 - Virtex-5 FXT - Missing constraint in Example Design UCF

Description

When when you generate a core for Virtex-5 FXT, there is a period constraint missing in the example design UCF.

Solution

The following constraint should be added to the ucf file: 

 

TIMESPEC "TS_recclk" = PERIOD "recclk_int" 153.6 MHz; 

 

This belongs below the line: 

NET "recclk_int" TNM_NET = "recclk_int";

AR# 32645
Date Created 05/01/2009
Last Updated 05/21/2014
Status Archive
Type General Article