AR #32651 - Spartan-6 - ISE Software 11.3 Update Known Issues related to Spartan-6 FPGA

AR#	32651
Part	FPGA-Spartan-CLB/Routing
Last Modified	2009-11-10 00:00:00.0
Status	Active
Keywords	ISE, 11.2, Update, known, issues

Solution

The following represent a collection of issues that have been identified in the 11.3 ISE design tools and are related to Spartan-6 FPGA. There might be issues which are present and are not listed here. If you discover an issue that is not on this list, please open a WebCase with Xilinx Support:
http://www.xilinx.com/support/

Due to the issues listed in this Answer Record (and other fixes being implemented), it is recommended that you update your software to the latest version when it becomes available.

General:
(Xilinx Answer 33505) Spartan-6 - Fix for issue: 11.2 General ES Patch for Spartan-6 FPGA results in EDK crash

Packaging
**(Xilinx Answer 33702) Spartan-6 - LX75 and LX75T I/O Connectivity Issue in ISE Design Suite 11.3

DCM and PLL:
(Xilinx Answer 33019) Spartan-6 Clocking - DCM_CLKGEN Spread Spectrum Clock Generation feature support

GTP Transceiver
(Xilinx Answer 33487) Spartan-6 GTP Transceiver - Known Issues and Answer Record List

MAP
(Xilinx Answer 33358) Spartan-6 FPGA MCB - "ERROR:Place:864" errors occur during PAR when data mask is disabled

PAR
(Xilinx Answer 33153) 11.2 Spartan-6 PAR - Incorrect "WARNING:ParHelpers:79" message

Timing:
(Xilinx Answer 32838) 11.1 Constraints Editor - Non-Clock nets are listed for Spartan-6 design
(Xilinx Answer 32954) 11.2 Timing - Derived clock report does not have clock name for Spartan-6 FPGA reference design

Simulation Libraries
(Xilinx Answer 33491) LogiCORE XAUI v9.1 - Timeout seen in Spartan-6 FPGA Example Design Timing Simulation

EDK
(Xilinx Answer 33385) 11.2 EDK, MPMC v5.02.a - Single PLB memory writes corrupted in Spartan-6 FPGA

BitGen:
(Xilinx Answer 33356) Spartan-6 FPGA MCB - X4 memory components are not supported until ISE Design Suite 11.4 (MIG 3.3)
(Xilinx Answer 33357) Spartan-6 FPGA MCB - Port 3 is not supported in read mode when all 6 ports are configured
(Xilinx Answer 33223) 11 EDK - "ERROR:PhysDesignRules:1690 - Incomplete PLL_ADV to PCC440 programming."

CORE Generator:
(Xilinx Answer 32815) Block Memory Generator v3.2 - Asynchronous reset not supported in Spartan-6 FPGA

Memory Interface Generator (MIG)
(Xilinx Answer 32641) MIG v3.1 - Release Notes and Known Issues for ISE Design Suite 11.3

LogiCORE IP
(Xilinx Answer 33393) LogiCORE Video Scaler v2.0 - When targeting Virtex-6 or Spartan-6 FPGAs using the pCore interface, why do I get an XST Compiler:410 error?
(Xilinx Answer 33486) LogiCORE XAUI v9.1 and RXAUI v1.1 - Update needed for reset logic in block level for Spartan-6 Device GTP and Virtex-6 Device GTX wrappers
(Xilinx Answer 33491) LogiCORE XAUI v9.1 - Timeout seen in Spartan-6 FPGA Example Design Timing Simulation
(Xilinx Answer 33492) LogiCORE XAUI v9.1 - Implementing Spartan-6 and Virtex-6 FPGA Examples Designs results in MAP errors for some device packages

** - Issues noted with " ** " were published as a Design Advisory.


Revision HIstory:
11/11/09 - Updated Known Issues with Design Advisory: (Xilinx Answer 33702).
09/16/09 - Initial Release of Known Issues for ISE 11.3