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AR# 32651

Spartan-6 - ISE Software 11 Update Known Issues related to Spartan-6 FPGA

Description

This Answer Record describes the Known Issues for the Spartan-6 FPGA generation used with the ISE Design Suite 11.

Solution

The following represent a collection of issues that have been identified in the 11.5 ISE Design Tools and are related to Spartan-6 FPGA.

There might be issues which are present and are not listed here. If you discover an issue that is not on this list, please open a Service Request with Xilinx Technical Support. 


It is strongly recommended that designs be re-synthesized (and IP cores re-implemented) when re-implementing for production using the software that has production status speed files for the target device.

This ensures that the changes to DRCs, timing models, clock topologies, and other fixes in software are picked up.



Block RAM
(Xilinx Answer 34533) Spartan-6 Block RAM Design Advisory - Address Space Overlap
(Xilinx Answer 34541) Spartan-6 Block RAM Design Advisory - 9K BRAM Simple Dual Port (SDP) Port Width Restriction
(Xilinx Answer 34659) Spartan-6 Block RAM - Output Register of BRAM does not Initialize Correctly After Initial Configuration
(Xilinx Answer 34712) Spartan-6 Block RAM Design Advisory- 9K Simple Dual Port (SDP) Block RAM Initialization Incorrect
(Xilinx Answer 34713) Spartan-6 Block RAM - INIT_FILE Attribute on 9K Block RAM Does Not Initialize Correctly
(Xilinx Answer 34714) Spartan-6 Block RAM - Data2Mem Does Not Support 9Kb Block RAMs
(Xilinx Answer 34803) Spartan-6 Block RAM - 9Kb Block RAM SRVAL/INIT Values Incorrect for Parity Bits
Clocking
(Xilinx Answer 34885) 11.4 Spartan-6 Place - LX25 device has BUFIO2 pin compatibility issue with other devices
(Xilinx Answer 34675) Spartan-6 - Low Power Devices Require an Additional Low Power Reset Circuit for DCM_SP and DCM_CLKGEN
(Xilinx Answer 34766) Spartan-6 PLL - Incorrect Compensation Mode Set
(Xilinx Answer 34767) Spartan-6 Clocking - Feedback Path From DCM or PLL Not Properly Routed

Power
(Xilinx Answer 34465) Spartan-6 - XC6SLX16, XC6SLX45, XC6SLX45T Maximum startup ICCINT
Timing
(Xilinx Answer 33808) SPI-3 Link Layer v7.1 - Some Spartan-6 FPGA designs might fail timing
EDK
(Xilinx Answer 33840) 11.4 EDK, XPS_LL_TEMAC_v2_03_a - Tactical patch to allow connection of external PCS/PMA core in Spartan-6 devices
ChipScope
(Xilinx Answer 33755) 11.x ChipScope Pro Inserter - Spartan-6 is shown as the device family when the project is Automotive or Low Power Spartan-6 FPGA
(Xilinx Answer 33843) 11.x ChipScope IBERT - Spartan-6 FPGA sweep test does not change sampling point

CORE Generator
(Xilinx Answer 33665) 11.4 CORE Generator - Why am I unable to select the -3 speed grade for the PCIe core generation for the Spartan-6 FPGA xc6slx45t part that is on the SP605 board?
Revision History
04/12/10 Added AR34885
03/25/10 Added AR34803
03/19/10 Added Block RAM section
03/16/10 ISE 11.5 Release. Added Issues For 11.5 SW. Removed issues fixed in 11.5.
02/08/10 Added Answer Record 34344
12/08/09 Initial 11.4 Release
AR# 32651
Date Created 05/05/2009
Last Updated 12/07/2015
Status Active
Type Known Issues
Devices
  • Spartan-6 LX
  • Spartan-6 LXT
Tools
  • ISE Design Suite - 11.5