We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 32654

10.1 EDK Sp3, plbv46_pci_v1_03_a - After PCI RST_n reset assertion, the PCI to PLB writes can be terminated and reset is needed to recover.


The failure mode is that after a PCI RST_n assertion, occasionally, depending on the clock phases, the PCI writes to PLB devices are terminated and the PCI device issues retry forever, until either the PCI or PLB reset is asserted. Note that PCI reads of PLB devices are functional.

This may occur 1 in 40 reset tries; the low probability of the failure does not suggest that it will happen in two sequential resets.


You can download the latest patch from:


- Please copy the "plbv46_master_v1_03_a" from the EDK build 'pcores' repository to your project local "pcores".

- Unzip and replace the "llink_wr_backend_async2.vhd" file in the your local "pcore" directory (i.e. under 'plbv46_master_v1_03_a\hdl\vhdl') with this latest file.

This issue is scheduled to be fixed in the "plbv46_master v1.04.a" and it will be included in the next version of the pci core.


AR# 32654
Date Created 05/05/2009
Last Updated 02/21/2013
Status Active
Type General Article