This README Answer Record contains installation instructions and a list of the issues fixed in ChipScope Pro Analyzer 11.5 Updates.
A successful installation of ChipScope Pro Analyzer 11.5 Update changes your software version number to 11.5.
The destination directory specified during the setup operation must contain an existing Xilinx ISE design tools installation.
NOTE: Any new device support not previously installed should first be installed before you add the Update.
Installation Instructions for ISE Design Suite 11.5
1. Download "Xilinx_11.5_ISE_DS_<platform>.tar" from:
http://license.xilinx.com/getLicense?group=esd_oms&tab=DownloadUpdates
2. Un-tar the archive. For more information about tar files, see (Xilinx Answer 32818).
3. Open the un-tarred archive and run "xsetup.(exe)".
4. Select the root location of ISE Design Suite as your destination directory (that is, C:\Xilinx\11.1 or /opt/Xilinx/11.1).
NOTE: Web XilinxUpdate can also be used to download and install ISE design tools updates by typing xilinxupdate into a terminal/command prompt or through ISE -> Help -> XilinxUpdate.
Installation Instructions for Standalone ChipScope 11.5
Windows Users
1. Download "Xilinx_11.5_cs_win(64).exe" from:
http://license.xilinx.com/getLicense?group=esd_oms&tab=DownloadUpdates
2. Launch Xilinx Update by double-clicking on the downloaded executable.
3. Select the location of ISE Design Suite Programming Tools as your destination directory (that is, C:\Xilinx\11.1\ChipScope).
Linux Users
1. Download "Xilinx_11.5_cs_lin(64).zip" from:
http://license.xilinx.com/getLicense?group=esd_oms&tab=DownloadUpdates
2. Unzip the archive. For more information about tar files, see (Xilinx Answer 32818).
3. Open the unzipped archive and run "xsetup" by typing ./xsetup to a terminal.
4. Select the location of ISE Design Suite Programming Tools as your destination directory (that is, /opt/Xilinx/11.1/ChipScope).
Known Issues for 11.2
(Xilinx Answer 31452) 10.1/11.x ChipScope Pro Analyzer IBERT - When I open the cable, I am asked to update my DRP settings, even though the design is unchangedResolved Issues for 11.2
(Xilinx Answer 32804) 10.1.03, 11.1 ChipScope Pro Analyzer, IBERT - The Pre-Emphasis and Differential output swing do not match the User Guide
(Xilinx Answer 32431) 11.1 ChipScope Pro Analyzer IBERT - Generation fails at MAP for designs on Virtex-5 LX20T device
(Xilinx Answer 31975) 10.1 ChipScope Pro Analyzer - My ATC2 Core cannot be detected
(Xilinx Answer 32434) 11.1 ChipScope Pro Analyzer - Analyzer does not recognize Partial Bit files
(Xilinx Answer 32501) ChipScope Pro Analyzer IBERT - 8b10b is only supported with the framed counter and User Pattern
(Xilinx Answer 32299) 11.1 ChipScope Pro Analyzer - Inserter "WARNING:sim:356 - The parameter "Exclude_From_Data_Storage_1" is disabled, its value will default from false to true"
(Xilinx Answer 32346) ChipScope Pro Analyzer - What do the "Configuration Status bits" mean?
Known Issues for 11.3
(Xilinx Answer 33242) 11.2 ChipScope Pro Analyzer IBERT - Virtex-6 FPGA - Moving the sampling point slider sets EYE_SCAN_MODE attribute auto to manual
(Xilinx Answer 32438) 11.x ChipScope Pro CORE Generator - The Trigger Port numbers are confusing
(Xilinx Answer 33241) 11.1/11.2 ChipScope Pro Analyzer - When loading a new project, some signals, buses, and trigger names may be carried over
(Xilinx Answer 32912) 11.2 ChipScope Analyzer - "ERROR:INTERNAL_ERROR:Portability:basutencodeimp.c:229:1.24"
(Xilinx Answer 32228) 10.1, 11.1, 11.2 ChipScope - "Error-[URMI] Instances with unresolved modules remain in the design"
(Xilinx Answer 31691) 10.1.03, 11.1, 11.2 ChipScope Pro - "ERROR: ChipScope Insertion failed"
(Xilinx Answer 31452) 10.1, 11.x ChipScope Pro IBERT - When I open the cable, I am asked to update the DRP settings, even though the design is unchanged
(Xilinx Answer 32911) 11.2 ChipScope Pro - ChipScope Analyzer cannot be viewed over Microsoft NetMeeting
(Xilinx Answer 33064) 10.1/11.1/11.2 ChipScope Pro - Analyzer - ERROR: Socket Open Failed. localhost/0:0:0:0:0:0:0:1:50001
(Xilinx Answer 31427) 10.1, 11.x ChipScope Pro - The CPU usage is high, and my PC slows down when I perform a capture in the Analyzer on my ILA
(Xilinx Answer 33338) 11.2/11.3/11.4 ChipScope Pro Analyzer - When I reconfigure with the same bit file, my buses are displayed incorrectly
(Xilinx Answer 33524) 11.3 ChipScope Pro IBERT - CORE Generator GUI crashes when I hit generate for my Virtex-6/Spartan-6 FPGA IBERT core
(Xilinx Answer 33604) 11.3 ChipScope Pro IBERT - "ERROR:sim - Error: Par failed. Timing for this design was not met. Reduce the number of GTs enabled...."
(Xilinx Answer 33701) 11.3 ChipScope IBERT - "ERROR:HDLCompiler:1318 - "<path>/xsdb_bus_controller.vhd" Line 416: Left bound value <15> of slice is out of range [7:0] of array <sl_sel_i>"
(Xilinx Answer 33708) 11.x ChipScope Pro Inserter - "ERROR:ProjectMgmt:387-TOE: ITclInterp::ExecuteCmd gave Tcl result 'can't read "lOutputFileList": no such variable'."
(Xilinx Answer 33754)11.3 ChipScope Pro - Coregen - Number of ATD pins available on ATC2 core does not match with the User Guide
(Xilinx Answer 33755) 11.x ChipScope Pro - Inserter - Spartan-6 is shown as the device family when the project is Automotive or Low Power Spartan-6
(Xilinx Answer 33794) 11.3 ChipScope - IBERT - Spartan-6 - ERROR: Internal Error - Callback for CseXsdb_setRegisters failed : java.lang.IllegalArgumentException: Non-positive period.
(Xilinx Answer 33823) 11.x ChipScope Pro - qvirtex5 - "ERROR:Pack:2811 - Directed packing was unable to obey the user design"
(Xilinx Answer 33843) 11.x ChipScope - IBERT - Spartan-6 - Sweep test does not change sampling point
Resolved Issues for 11.3
(Xilinx Answer 33041) 11.1/11.2 ChipScope Pro - The Analyzer GUI hangs when I try to "Save Project"
(Xilinx Answer 31788) 11.x ChipScope Pro - "ERROR:MapLib:990 - Map has detected that you are using ChipScope Pro cores generated prior to version 10.1..."
(Xilinx Answer 32433) 11.1, 11.2 ChipScope Pro Analyzer - Auto Bus Creation creates 1-bit buses
(Xilinx Answer 32432) 11.1, 11.2 ChipScope Pro Analyzer - Auto Bus Creation does not work for VIO
(Xilinx Answer 32783) 11.2 ChipScope Pro IBERT - "ERROR:sim - Error: map failed on chipscope_ibert. ERROR:Pack:1107..."
(Xilinx Answer 32910) 11.2 ChipScope Pro IBERT - "ERROR - Device 1 Unit 1000"
(Xilinx Answer 33104) 11.2 ChipScope Pro IBERT - When I regenerate my IBERT core using the CORE Generator generated XCO, the line rate is not set
(Xilinx Answer 33041) 11.1/11.2 ChipScope Pro - The Analyzer GUI hangs when I try to "Save Project"
(Xilinx Answer 33141) ChipScope/iMPACT - Operations fail when the Cable is operated at 24 MHz
11.4 Known Issues
(Xilinx Answer 33701) 11.3 ChipScope IBERT - "ERROR:HDLCompiler:1318 - "<path>/xsdb_bus_controller.vhd" Line 416: Left bound value <15> of slice is out of range [7:0] of array <sl_sel_i>"
(Xilinx Answer 33041) 11.1/11.2 ChipScope Pro - The Analyzer GUI hangs when I try to "Save Project"
(Xilinx Answer 32438) 11.x ChipScope Pro CORE Generator - The Trigger Port numbers are confusing
(Xilinx Answer 33755) 11.x ChipScope Pro Inserter - Spartan-6 is shown as the device family when the project is Automotive or Low Power Spartan-6 FPGA
(Xilinx Answer 33554) ChipScope Pro analyzer - WARNING:PhysDesignRules:372 - Gated clock. Clock net icon_<netname> is source by a combinatorial pin
(Xilinx Answer 33241) 11.1/11.2 ChipScope Pro Analyzer - When loading a new project, some signals, buses, and trigger names may be carried over
(Xilinx Answer 33552) ChipScope Pro analyzer - When I use the trigger sequencer with a counter I see unexpected results
(Xilinx Answer 31788) 11.x ChipScope Pro - "ERROR:MapLib:990 - Map has detected that you are using ChipScope Pro cores generated prior to version 10.1..."
(Xilinx Answer 33598) ChipScope Pro Analyzer - Programming Cable connection fails and "INFO: Cable connection failed." appears in the console
(Xilinx Answer 32912) 11.2 ChipScope Analyzer - "ERROR:INTERNAL_ERROR:Portability:basutencodeimp.c:229:1.24"
(Xilinx Answer 32228) 10.1, 11.1, 11.2 ChipScope - "Error-[URMI] Instances with unresolved modules remain in the design"
(Xilinx Answer 33599) 11.x ChipScope Pro - "csejtag - The application failed to start because libCseCore.dll was not found. Re-installing the application may fix this problem."
(Xilinx Answer 19337) ChipScope Pro - "INFO: Found 0 Core Units in the JTAG device Chain"
(Xilinx Answer 32911) 11.2 ChipScope Pro - ChipScope Analyzer cannot be viewed over Microsoft NetMeeting
(Xilinx Answer 33524) 11.3 ChipScope Pro - IBERT - CORE Generator GUI crashes when I hit generate for my Virtex-6/Spartan-6 IBERT core
(Xilinx Answer 33064) 10.1/11.1/11.2 ChipScope Pro - Analyzer - "ERROR: Socket Open Failed. localhost/0:0:0:0:0:0:0:1:50001"
(Xilinx Answer 33754) 11.3 ChipScope Pro - Number of ATD pins available on ATC2 core does not match with the User Guide
(Xilinx Answer 33338) 11.2/11.3/11.4 ChipScope Pro Analyzer - When I reconfigure with the same bit file, my buses are displayed incorrectly
(Xilinx Answer 33823) 11.x ChipScope Pro - qvirtex5 - "ERROR:Pack:2811 - Directed packing was unable to obey the user design"
(Xilinx Answer 33824) 11.4 ChipScope, IBERT GTH - "ERROR:sim - Error: ngdbuild failed on prime_top. ERROR:ConstraintSystem:58 "
11.4 Resolved Issues
(Xilinx Answer 33242) 11.2, 11.3 ChipScope Pro Analyzer IBERT - Moving the sampling point slider sets EYE_SCAN_MODE attribute auto to manual
(Xilinx Answer 33553) 11.3 ChipScope Pro Analyzer - Trigger fails when I use range or extended trigger match units on Spartan-6 FPGA
(Xilinx Answer 33604) 11.3 ChipScope Pro, IBERT - "ERROR:sim - Error: Par failed. Timing for this design was not met. Reduce the number of GTs enabled...."
(Xilinx Answer 33794) 11.3 ChipScope, IBERT - Spartan-6 "ERROR: Internal Error - Callback for CseXsdb_setRegisters failed : java.lang.IllegalArgumentException: Non-positive period."
11.5 Known Issues
(Xilinx Answer 33701) 11.3 ChipScope IBERT - "ERROR:HDLCompiler:1318 - "<path>/xsdb_bus_controller.vhd" Line 416: Left bound value <15> of slice is out of range [7:0] of array <sl_sel_i>"
(Xilinx Answer 33041) 11.1/11.2 ChipScope Pro - The Analyzer GUI hangs when I try to "Save Project"
(Xilinx Answer 32438) 11.x ChipScope Pro CORE Generator - The Trigger Port numbers are confusing
(Xilinx Answer 33755) 11.x ChipScope Pro Inserter - Spartan-6 is shown as the device family when the project is Automotive or Low Power Spartan-6 FPGA
(Xilinx Answer 33554) ChipScope Pro analyzer - WARNING:PhysDesignRules:372 - Gated clock. Clock net icon_<netname> is source by a combinatorial pin
(Xilinx Answer 33241) 11.1/11.2 ChipScope Pro Analyzer - When loading a new project, some signals, buses, and trigger names may be carried over
(Xilinx Answer 33552) ChipScope Pro analyzer - When I use the trigger sequencer with a counter I see unexpected results
(Xilinx Answer 31788) 11.x ChipScope Pro - "ERROR:MapLib:990 - Map has detected that you are using ChipScope Pro cores generated prior to version 10.1..."
(Xilinx Answer 33598) ChipScope Pro Analyzer - Programming Cable connection fails and "INFO: Cable connection failed." appears in the console
(Xilinx Answer 32912) 11.2 ChipScope Analyzer - "ERROR:INTERNAL_ERROR:Portability:basutencodeimp.c:229:1.24"
(Xilinx Answer 32228) 10.1, 11.1, 11.2 ChipScope - "Error-[URMI] Instances with unresolved modules remain in the design"
(Xilinx Answer 33599) 11.x ChipScope Pro - "csejtag - The application failed to start because libCseCore.dll was not found. Re-installing the application may fix this problem."
(Xilinx Answer 19337) ChipScope Pro - "INFO: Found 0 Core Units in the JTAG device Chain"
(Xilinx Answer 32911) 11.2 ChipScope Pro - ChipScope Analyzer cannot be viewed over Microsoft NetMeeting
(Xilinx Answer 33524) 11.3 ChipScope Pro - IBERT - CORE Generator GUI crashes when I hit generate for my Virtex-6/Spartan-6 IBERT core
(Xilinx Answer 33064) 10.1/11.1/11.2 ChipScope Pro - Analyzer - "ERROR: Socket Open Failed. localhost/0:0:0:0:0:0:0:1:50001"
(Xilinx Answer 33754) 11.3 ChipScope Pro - Number of ATD pins available on ATC2 core does not match with the User Guide
(Xilinx Answer 33338) 11.2/11.3/11.4 ChipScope Pro Analyzer - When I reconfigure with the same bit file, my buses are displayed incorrectly
(Xilinx Answer 33823) 11.x ChipScope Pro - qvirtex5 - "ERROR:Pack:2811 - Directed packing was unable to obey the user design"
(Xilinx Answer 33824) 11.4 ChipScope, IBERT GTH - "ERROR:sim - Error: ngdbuild failed on prime_top. ERROR:ConstraintSystem:58 "
(Xilinx Answer 34669) 11.x ChipScope - Analyzer - IBERT - ERROR:XSDB Master could not reset the System Clock. The System Clock is not locked. The System Clock is not running
(Xilinx Answer 34674) 11.x ChipScope - IBERT - Virtex-6 GTX: Coregen does not list upper GTXE1 quads of SX475T and LX550T
(Xilinx Answer 34581) 11.x ChipScope Pro - BUFG insertion is always enabled on the JTAG clock for the ICON core
(Xilinx Answer 34683) 11.x ChipScope - Virtex-6 - IBERT parameter sweep tests show errors in the middle of the eye
(Xilinx Answer 34901) 11.5 ChipSocpe - IBERT - The following error has occurred. Error: map failed on chipscope_ibert. ERROR:PhysDesignRules:1997 - The computed value for the VCO operating frequency of MMCM_ADV instance