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AR# 32661

Virtex-6 CXT - What is the Virtex-6 CXT device family?


The 11.2 ISE Design Suite shows a part selection for Virtex-6 CXT FPGA. What is this family and where can I obtain more information?


Virtex-6 CXT FPGAs provide designers needing cost-optimized 3.75 Gb/s transceiver performance an optimized ratio of built-in system-level blocks. These include 36 Kb block RAM/FIFOs, up to 15 Mb block RAM, up to 768 DSP48E1 slices, enhanced mixed-mode clock management blocks, advanced configuration options, Gen 1 PCI Express compatible integrated blocks, a tri-mode Ethernet media access controller (MACs), up to 241K logic cells, and strong IP support.

Customers needing higher logic or transceiver performance, more block RAM, additional DSP capability, Gen 2 PCI Express, additional Ethernet MACs, or over 241K logic cells should use the Virtex-6 LXT family instead.

If Spartan-6 LXT FPGAs capabilities are sufficient (speed, DSP count, block RAM size, logic count, transceivers), then Xilinx recommends the Spartan-6 family as the lower cost option.

The Virtex-6 CXT FPGA Data Sheet is available at:

For Virtex-6 CXT FPGA related 11.2 software/IP Known Issues, see (Xilinx Answer 32864).
For Virtex-6 family related 11.2 software/IP Known Issues, see (Xilinx Answer 32939).
AR# 32661
Date Created 06/22/2009
Last Updated 12/15/2012
Status Active
Type General Article
  • Virtex-6 CXT
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2