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AR# 32694

Aurora 8B10B v4.1 - "ERROR:HDLCompilers:28" when synthesizing a core targeting Virtex-5 TXT


When I generate an Aurora Core for the Virtex-5 TXT, if I use the right-hand column of GTX transceivers, the GT wrapper file is incorrect. I receive errors similar to the following in synthesis:

"ERROR:HDLCompilers:28 - "../example_design/gt/<core_name>_transceiver_wrapper.v[hd]" line ### 'CHAN_BOND_MODE_1_LANEX' has not been declared"


The Aurora Core's wizard does not correctly propagate lane assignments to the XCO file for generation. Lane 1 is assigned twice in the XCO file (there is an extra assignment of lane 1 in the left column), resulting in an incorrect number of GTX instantiations. There are two possible work-arounds:

Option 1:

Generate the core with the same relative placement of the GTX transceivers in the left column, then change the UCF file that is provided to reflect the desired GTX locations.

Option 2:

Generate the core with the desired GTX lane assignments in the right-hand column, then edit the XCO file that is generated with the core such that there is only one "lane 1" assignment.


CSET c_gt_loc_24=1 => CSET c_gt_loc_24=X

Then, regenerate the core by running CORE Generator in batch mode.

Command prompt example:

coregen -b <modified_xco_name>.xco

This problem is scheduled to be fixed in v4.2 of the core.

Revision History

5/12/09 - Initial Release

AR# 32694
Date 12/15/2012
Status Active
Type General Article