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AR# 32707

12.1 Timing Analyzer - IODELAY Min, Maximum Delay information

Description


The Virtex-5 FPGA data sheet mentions to look at the Timing Analyzer report for the calculation part of the delay in relation to IODELAY block. However, the same delay information in the speed print indicates that the MIN delay is more than the MAX delay.
Why the discrepancy?

Solution

True, the speed print actually mentions that the MIN delay is larger than the MAX delay.MIN delay adjusts hold time, whereas, MAX delay adjusts setup time.The speed file manipulates the delay values to ensure that the implementation tools match what is characterized in the hardware.
AR# 32707
Date Created 06/05/2009
Last Updated 05/19/2012
Status Active
Type Known Issues
Devices
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • More
  • Virtex-5 SXT
  • Virtex-5 TXT
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Tools
  • ISE - 10.1
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • More
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
  • ISE Design Suite - 13.1
  • Less