AR #32717 - XtremeDSP Development Kit-IV ROHS Compliant - Why do I see a reduced SFDR performance on the output of my ADCs, than is described in the XtremeDSP Development Kit-IV User Guide?
XtremeDSP Development Kit-IV ROHS Compliant - Why do I see a reduced SFDR performance on the output of my ADCs, than is described in the XtremeDSP Development Kit-IV User Guide?
| AR# | 32717 |
| Part | HW-DevBoard DSP |
| Last Modified | 2009-06-26 00:00:00.0 |
| Status | Active |
| Keywords | USB, PCI, Virtex-4, SX35, RoHS, ADC, SFDR, spurs, spikes |
Description
Keywords: USB, PCI, Virtex-4, SX35, RoHS, ADC, SFDR, spurs, spikes
Why do I see reduced SFDR performance on the output of my ADCs than is described in the XtremeDSP Development Kit-IV User Guide?
Solution
It was discovered that the drive strength on the I/O driving the ADCs was not strong enough.This issue should only apply to the XtremeDSP Development Kit-IV RoHS compliant edition.
A new bitstream and source code for the Virtex-II Clock FPGA can be obtained from the Nallatech Support Lounge for the XtremeDSP Development Kit-IV.
http://www.nallatech.com
- See the XtremeDSP Clock Driver Update (May, 8 2009).