Why do I see reduced SFDR performance on the output of my ADCs than is described in the XtremeDSP Development Kit-IV User Guide?
It was discovered that the drive strength on the I/O driving the ADCs was not strong enough.
This issue should only apply to the XtremeDSP Development Kit-IV RoHS compliant edition.
A new bitstream and source code for the Virtex-II Clock FPGA can be obtained from the Nallatech Support Lounge for the XtremeDSP Development Kit-IV.
- See the XtremeDSP Clock Driver Update (May, 8 2009).