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AR# 32731

11 EDK - The indices are not what I would expect for the MPMC when I change from the default data width to a lower data width

Description

When I change the data width of the MPMC Core in the IP Configuration window, the resulting indices in the MHS file are: 

 

Before (64 bits): 

fpga_0_DDR2_SDRAM_DDR2_DQ_pin [63:0] 

 

After (32 bits): 

fpga_0_DDR2_SDRAM_DDR2_DQ_pin [63:94] 

 

And the other buses that are affected by the data width change also have unusual indices.

Solution

Logically, the connections are fine, although it does make the wiring of the MPMC confusing. The work-around is to manually change the odd indices in the MHS file to more "normal" looking indices: 

 

Before (32 bits): 

fpga_0_DDR2_SDRAM_DDR2_DQ_pin [63:94] 

 

After (32 bits): 

fpga_0_DDR2_SDRAM_DDR2_DQ_pin [31:0] 

 

This problem has been fixed in EDK 11.3, available at: 

http://www.xilinx.com/support/download/index.htm

AR# 32731
Date Created 05/20/2009
Last Updated 05/21/2014
Status Archive
Type General Article