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AR# 32741

Endpoint Block Plus Wrapper v1.11 for PCI Express - Release Notes and Known Issues for ISE Design Suite 11.2

Description


This Release Notes and Known Issues Answer Record is for the Endpoint Block Plus Wrapper v1.11, released in ISE Design Suite 11.2, and contains the following information:

- General Information
- New Features
- Bug Fixes
- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Solution


General Information

The LogiCORE Endpoint Block Plus for PCI Express requires a license to generate and implement the core. There is no charge for this license.

To obtain the license, visit the product lounge at:
http://www.xilinx.com/products/ipcenter/V5_PCI_Express_Block_Plus.htm

New Features

- ISE 11.2 software support
- 2-lane product support
- New input pin fast_train_simulation_only to decrease simulation time

Resolved Issues

CR 493708 - Transitioning from D0 to D3hot and back caused the core transmitter to lock-up
Issue resolved where transitioning the Endpoint from D0 to D3hot and back to D0 caused the core transmitter to lock-up.
Fixed in v1.10.1 and included in v1.11.

CR 478312 - GUI Settings to control GTX attributes do not match GTX spec
Issue resolved where the GUI settings to control GTX attributes did not match the GTX specification.

CR 504873 - Endpoint transmitter may lock-up when link partner advertises non-infinite Completion credits
Link partner advertisement of Finite Completion Credits such that the Endpoint is Data credit limited could cause the Endpoint transmitter to lock-up.
Fixed in v1.10.1 and included in v1.11.

CR 509028, 506462 - Completion Streaming can cause Endpoint Receiver buffer Overflow
Packet type switching when in Completion Streaming mode may cause the Endpoint Receiver buffer to Overflow.
Fixed in v1.10.1 and included in v1.11.

CR 436916 - Per-Vector Masking bit Set in MSI Control Register
Issue resolved where the Per-Vector Masking bit in the MSI Control Register was set, though Per Vector Masking is not supported.
Fixed in v1.10.1 and included in v1.11.

CR 513886 - Endpoint Block Plus does not work in asynchronous mode
Issue resolved where the Endpoint Block Plus core did not work when the reference clock between the PC/Motherboard and the Endpoint were different.

CR 518971 - PIO design causing BitGen DRC failures
Issue resolved where dangling block RAM CASCADE Inputs in the PIO design were causing BitGen DRC failures.

Known Issues
There are three main components to the Endpoint Block Plus Wrapper for PCI Express:

- Virtex-5 FPGA Integrated Block for PCI Express
- Virtex-5 FPGA GTP/GTX Transceivers
- Block Plus Wrapper FPGA fabric logic

There are known issues and restrictions for each of these components, as described below:

Virtex-5 FPGA Integrated Block for PCI Express Known Restrictions
There are three main components to the Endpoint Block Plus Wrapper for PCI Express:

- Virtex-5 FPGA Integrated Block for PCI Express
- Virtex-5 FPGA GTP/GTX Transceivers
- Block Plus Wrapper FPGA fabric logic

The known issues for the integrated block and GTP/GTX transceivers are found in the Block Plus core user guide :
http://www.xilinx.com/support/documentation/ipbusinterfacei-o_pci-express_v5pciexpressblockplus.htm

Block Plus Wrapper FPGA fabric logic

(Xilinx Answer 31211) - Endpoint Block Plus Wrapper v1.11 for PCI Express - Link transitioning to L0s causes BAR settings to reset

(Xilinx Answer 31646) - Endpoint Block Plus Wrapper v1.11 for PCI Express - Dual Core UCF problems

(Xilinx Answer 31647) - Endpoint Block Plus Wrapper v1.11 for PCI Express - Dual core implement_dual.bat missing

(Xilinx Answer 31850) - Endpoint Block Plus Wrapper v1.11 for PCI Express - Simulation testbench writes to incorrect address for device control register

(Xilinx Answer 32091) - Endpoint Block Plus Wrapper v1.11 for PCI Express - Downstream port model drops completions with length 64 bytes and greater

(Xilinx Answer 32727) - Endpoint Block Plus Wrapper v1.11 for PCI Express - MAP failing to complete due to predictable IP placement constraints

(Xilinx Answer 32946) - Endpoint Block Plus Wrapper v1.11 for PCI Express - Syntax error in x1 board_dual.v Causes Simulation Failures

(Xilinx Answer 33411) - Endpoint Block Plus Wrapper v1.11 for PCI Express - After Warm Reset, TX Direction Stalls Forever Due to Deassertion of trn_tdst_rdy_n

(Xilinx Answer 33421) - Endpoint Block Plus Wrapper v1.11 for PCI Express - Core generated for x2 lanes, Virtex-5 FXT or TXT, will not link up

Revision History
09/22/2009 - Added 33421, Removed reference to UG493 and replaced with 341
09/08/2009 - Added 33411
06/24/2009 - Initial Release
AR# 32741
Date Created 06/12/2009
Last Updated 12/15/2012
Status Active
Type General Article
IP
  • Endpoint Block Plus Wrapper for PCI Express