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AR# 32742

Virtex-6 Integrated Block Wrapper v1.2 and v1.2.1 for PCI Express - Release Notes and Known Issues for ISE Design Suite 11.2

Description


This Release Notes and Known Issues Answer Record is for the Virtex-6 Integrated Block Wrapper v1.2 and v1.2.1 for PCI Express, released in ISE Design Suite 11.2, and it contains the following information:

- General Information
- New Features
- Bug Fixes
- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Solution


General Information

The Virtex-6 Integrated Block Wrapper for PCI Express requires a license to generate and implement the core. There is no charge for this license.

To obtain the license, visit the product lounge at:
http://www.xilinx.com/products/ipcenter/V6_PCI_Express_Block.htm

IMPORTANT NOTE: There is a v1.2.1 patch available in (Xilinx Answer 33042). This patch fixes issues listed below as (Xilinx Answer 32918), (Xilinx Answer 32935), (Xilinx Answer 33046), (Xilinx Answer 33047), (Xilinx Answer 33048), and (Xilinx Answer 33049).

New Features

- ISE 11.2 software support
- Support for the full Xilinx implementation and simulation flow, including bitstream generation
- Support for 8-lane Gen2 (128-bit interface) operation

Resolved Issues

CR 510818 - Transmit amplitude settings not compliant with the PCI Express Base Specification rev 2.0
Issue resolved in the Virtex-6 GTXE1 wrapper, where the PMA settings for transmit amplitude were non-compliant with the PCI Express Base Specification rev 2.0.

CR 510778 - XCF file not accounting for non-default User-Interface frequency
Issue resolved where the delivered XCF file did not account for non-default User-Interface frequency.

CR 509311 - Receiver Buffer Settings (block RAM Configurations) in the generated design not matching the GUI selections.
Issue resolved where the Receiver Buffer Settings -VC0_RX_RAM_LIMIT in the generated design was larger than the GUI selection.

Resolved in v1.2.1

CR 522593 - trn_reof_n assertion without a trn_rsof_n assertion on Receive Transaction Interface in the 8-lane Gen2 product.
Issue resolved where trn_reof_n could assert without a trn_rsof_n assertion in the 8-lane Gen2 product, when receiving back-to-back Transactions.

CR 524324 - Transaction Packet dropped on transmit when buffers are full, in the 8-lane Gen2 product.
Issue resolved where transaction packets could be dropped if the user transmitted packets when the transmit buffer was full.

CR 525136 - trn_teof_n input to the PCIe Integrated Block not asserted in conjunction with trn_tsrc_dsc_n, in the 8-lane Gen2 product.
Issue resolved where the 8-lane Gen2 product was not asserting the trn_teof_n input to the PCIe Integrated Block along with trn_tsrc_dsc_n assertion.

CR 525709 - cfg_interrupt_n asserted for extra cycles after cfg_interrupt_rdy_n, in the 8-lane Gen2 product.
Issue resolved where the 8-lane Gen2 product asserted the cfg_interrupt_n input to the PCIe Integrated Block for extra clock cycles after the PCIe Integrated Block asserted cfg_interrupt_rdy_n

CR 525691- De-assertion of trn_tsrc_rdy_n along with assertion of trn_teof_n when concurrent with an internally generated transaction, in the 8-lane Gen2 product, could cause core transmitter to lock-up.
Issue resolved where the 8-lane Gen2 product transmitter could lock-up on de-assertion of trn_tsrc_rdy_n along with assertion of trn_teof_n, when the Integrated Block for PCI Express is generating a transaction.

CR 523072 - Incorrect UCF path in implement.bat file.
Issue resolved where the relative path to the UCF in implement.bat was incorrect, when design is generated and implemented on Windows operating systems.

Known Issues

Virtex-6 solutions are pending hardware validation.

(Xilinx Answer 32914) - Virtex-6 Integrated Block Wrapper v1.2 for PCI Express - Error in generating core from ISE New source Wizard

(Xilinx Answer 32915) - Virtex-6 Integrated Block Wrapper v1.2 for PCI Express - Use of trn_rnp_ok_n not supported for the 8-lane Gen 2 Integrated Block Mode

(Xilinx Answer 32918) - Virtex-6 Integrated Block Wrapper v1.2 for PCI Express - In x8 Gen 2 mode, trn_reof_n May Assert Without an Associated trn_rsof_n Assertion. Fixed in v1.2.1.

(Xilinx Answer 32921) Virtex-6 Integrated Block Wrapper v1.2 for PCI Express - In x8 Gen 2 Mode, using 512 byte MPS may cause timing failures.

(Xilinx Answer 32923) - Virtex-6 Integrated Block Wrapper v1.2 for PCI Express - Programmed Power Management Mode (PPM) L1 State not supported in x8 Gen 2 Mode

(Xilinx Answer 32931) - Virtex-6 Integrated Block Wrapper v1.2 for PCI Express - Non-default User Interface Frequency not supported when the ML605 Development Board option is selected

(Xilinx Answer 32932) - Virtex-6 Integrated Block Wrapper v1.2 for PCI Express - VHDL Example Design and Testbench not available

(Xilinx Answer 32933) - Virtex-6 Integrated Block Wrapper v1.2 for PCI Express - Root Port Operation not supported in this release

(Xilinx Answer 32934) - Virtex-6 Integrated Block Wrapper v1.2 for PCI Express - 250 MHz Reference Clock Required for GEN 2 Mode of Operation

(Xilinx Answer 32935) - Virtex-6 Integrated Block Wrapper v1.2 for PCI Express - Incorrect path to UCF file in implement.bat file. Fixed in v1.2.1.

(Xilinx Answer 33046) Virtex-6 Integrated Block Wrapper v1.2 for PCI Express - In x8 Gen 2 Mode, TLP May be Dropped on Transmit Interface when Buffers are Full. Fixed in v1.2.1.

(Xilinx Answer 33047) Virtex-6 Integrated Block Wrapper v1.2 for PCI Express - In x8 Gen 2 Mode, on Block Interface trn_teof_n Not Asserting With trn_tsrc_dsc_n. Fixed in v1.2.1.

(Xilinx Answer 33048) Virtex-6 Integrated Block Wrapper v1.2 for PCI Express - In x8 Gen 2 Mode, on Block Interface cfg_interrupt_n Asserts for Extra Cycles After cfg_interrupt_rdy_n. Fixed in v1.2.1.

(Xilinx Answer 33049) Virtex-6 Integrated Block Wrapper v1.2 for PCI Express - In x8 Gen 2 Mode, Transmitter Lockup due to De-assertion of trn_tsrc_rdy_n Along with Assertion of trn_teof_n Concurrent with Internally Generated Transaction . Fixed in v1.2.1.

(Xilinx Answer 33106) Virtex-6 Integrated Block Wrapper v1.2 for PCI Express - ModelSim simulation does not show all signals in hierarchy

(Xilinx Answer 33127) Virtex-6 Integrated Block Wrapper v1.2 for PCI Express - UCF constraint for sys_clk incorrect for ML605


Revision History
07/13/2009 - Added AR 33127 to Known Issues
07/08/2009 - Added AR 33106 to Known Issues
06/25/2009 - Added v1.2.1 patch and ARs 33046, 33047, 33048, and 33049.
06/24/2009 - Initial Release
AR# 32742
Date Created 06/11/2009
Last Updated 12/15/2012
Status Active
Type General Article
IP
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )