Spartan-6 FPGA Integrated Block Wrapper v1.1 for PCI Express - Release Notes and Known Issues for ISE Design Suite 11.2
Description
This Release Notes and Known Issues Answer Record is for the Spartan-6 FPGA Integrated Block Wrapper v1.2 for PCI Express, released in ISE Design Suite 11.2, and contains the following information:
- General Information
- New Features
- Bug Fixes
- Known Issues
For installation instructions, general CORE Generator interface known issues, and design tools requirements, see the IP Release Notes Guide:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf
Solution
New Features
-NA
Resolved Issues
-NA
Known Issues
Spartan-6 FPGA solutions are pending hardware validation. VHDL support for the core will be added in a future release (tentatively scheduled for 11.3).
(Xilinx Answer 32865) - Spartan-6 FPGA Integrated Block Wrapper v1.1 for PCI Express - Clock-to-out delay required on cfg_interrupt_n for simulation
(Xilinx Answer 32867) - Spartan-6 FPGA Integrated Block Wrapper v1.1 for PCI Express - Designs which use the cfg_pm_wake_n input to generate a PME event should implement a timeout counter
Revision History
09/09/2009 - Removed 32866 -" Designs which use Multi-Vector MSI should check the number of allocated vectors before generating an MSI interrupt"; issue does not apply to endpoints.
08/17/2009 - Added information about VHDL support
06/24/2009 - Initial Release
Applies To
IP
- Spartan-6 FPGA Integrated Endpoint Block for PCI Express