This Release Notes and Known Issues Answer Record is for the Spartan-6 GTP Transceiver Wizard v1.2 and contains the following information:
- New Features
- Bug Fixes
- Known Issues
1. INTRODUCTION
For the most recent updates to the IP installation instructions for this core, please go to:
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
For system requirements:
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
This file contains release notes for the Xilinx Spartan-6 FPGA GTP Transceiver Wizard v1.2. For the latest core updates, see the product page at:
http://www.xilinx.com/products/intellectual-property/S6_FPGA_GTP_Transceiver_Wizard.htm
2. NEW FEATURES
- Implementation support for LX25T, LX45T, LX100T and LX150T
- For best results, use one of the available protocol templates sRIO, OBSAI, CPRI, DisplayPort protocol templates use 4-byte datapath width and HD-SDI, PCI Express protocol templates use 2-byte datapath width
3. RESOLVED ISSUES
- New directory structure for the generated example design. Please refer to the Getting Started Guide (UG546) for additional information
4. KNOWN ISSUES
The following are known issues for v1.2 of this core at time of release:
- Synplify Pro not supported for synthesis
- RST not held for 3 CLKIN cycles simulation warning. Please see AR 32230 for more information.
- May observe X's and timing simulation failures when doing back annotated simulation when using either the tx_sync deskew module.
- Spartan-6 solutions are pending hardware validation
The most recent information, including known issues, workarounds, and resolutions for this version is provided in the release notes Answer Record for the ISE 11.2 IP Update at
http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf
5. TECHNICAL SUPPORT
To obtain technical support, create a WebCase at www.xilinx.com/support. Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used according to the guidelines described in the core documentation, and cannot guarantee timing, functionality, or support of this product for designs that do not follow specified guidelines.
6. CORE RELEASE HISTORY
Date By Version Description
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06/24/2009 Xilinx, Inc. 1.2 11.2 Release
04/24/2009 Xilinx, Inc. 1.1 Initial release
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