LogiCORE IP Video Timing Controller - Release Notes and Known Issues
Description
This Answer Record contains the Release Notes and Known Issues for the CORE Generator software and LogiCORE IP Video Timing Controller. The following information is listed for each version of the core:
- New Features
- Bug Fixes
- Known Issues
http://www.xilinx.com/products/ipcenter/EF-DI-VID-TIMING.htm
Solution
General LogiCORE IP Video Timing Controller Issues- N/A
LogiCORE IP Video Timing Controller v3.0
- Initial Release in ISE 13.2 software
(*)To access these devices in the ISE Design Suite, contact your Xilinx FAE.
- Zynq-7000*
- Virtex-7
- Virtex-7 XT (7vx485t)
- Virtex-7 -2L
- Kintex-7
- Kintex-7 -2L
- Virtex-6 XC CXT/LXT/SXT/HXT
- Virtex-6 XQ LXT/SXT
- Virtex-6 -1L XC LXT/SXT
- Virtex-6 -1L XQ LXT/SXT
- Spartan-6 XC LX/LXT
- Spartan-6 XA LX/LXT
- Spartan-6 XQ LX/LXT
- Spartan-6 -1L XC LX
- Spartan-6 -1L XQ LX
- Virtex-5 XC LX/LXT/SXT/TXT/FXT
- Virtex-5 XQ LX/LXT/SXT/FXT
- Spartan-3A DSP
New Features
- Replaced PLB processor interface with AXI4-Lite interface.
- Moved Interrupt Controller to Address offset 0x200 instead of 0x100 for pCore
- Detection Status Registers readable in pCore
- Added "OPTION USAGE_LEVEL = BASE_USER" tp pCore MPD file
- Resolved detection interrupt issues
- (Xilinx Answer 38546) Why are the number of lines per frame being incorrectly detected?
- N/A
There was a v2.1 Rev2 patch available in (Xilinx Answer 35096). This patch was intended to fix issues listed below as (Xilinx Answer 38545), and (Xilinx Answer 38546).
- Initial Release in ISE 11.4 software
- Support for Generating Blanks from Syncs
- Support for Detecting Video Formats without blanks (sync/active_video) only
- Moved Interrupt Controller to Address offset 0x200 instead of 0x100 for pCore
- (Xilinx Answer 35436) Why am I having problems reading the Interrupt Status Registers?
- Detection Status Registers readable in pCore
- Added "OPTION USAGE_LEVEL = BASE_USER" tp pCore MPD file
- Resolved detection interrupt issues
- (Xilinx Answer 33829) Why are the detection ports still in the VHO file, when I did not select them in the core generation GUI?
- (Xilinx Answer 33830) Why do I see a mismatch between the behavioral simulation and the post-implementation gate level simulation results, when using the default GUI Values for Max Clock Per Line and the Max Lines Per Frame?
- (Xilinx Answer 35039) Why is the captured value for the vertical timing incorrect, or why is the status register not being updated, when targeting Spartan-6 or Virtex-6?
- (Xilinx Answer 38729) Why does the Video Timing Controller pCore fail to generate in EDK with an XST error?
- (Xilinx Answer 38545) Why is the Video Timing Controller so large when using the pCore interface?
- (Xilinx Answer 38546) Why are the number of lines per frame being incorrectly detected?
- (Xilinx Answer 39413) What signals are needed for the timing to be correctly detected and regenerated?
LogiCORE IP Video Timing Controller v2.0
- Initial Release in ISE 11.4 software
New Features
- Support for Spartan-6 FPGA
- Support for Virtex-6 FPGA
- EDK pCore option can now be generated from the CORE Generator software
- (Xilinx Answer 32913) Why do some Max Lines Per Frame values cause an "XST failed for v_timebase_v1_0" error during generation?
- (Xilinx Answer 33829) Why are the detection ports still in the VHO file, when I didn't select them in the core generation GUI?
- (Xilinx Answer 33830) Why do I see a mismatch between the behavioral simulation and the post-implementation gate level simulation results, when using the default GUI Values for Max Clock Per Line and the Max Lines Per Frame?
- (Xilinx Answer 35436) Why am I having problems reading the Interrupt Status Registers?
- (Xilinx Answer 35039) Why is the captured value for the vertical timing incorrect, or why is the status register not being updated, when targeting Spartan-6 or Virtex-6 FPGA?
- (Xilinx Answer 38729) Why does the Video Timing Controller pCore fail to generate in EDK with an XST error?
- (Xilinx Answer 39413) What signals are needed for the timing to be correctly detected and regenerated?
LogiCORE IP Video Timing Controller v1.0
- Initial Release in ISE 11.2 software
New Features
- Support for video frame sizes up to 4096 x 4096
- Direct regeneration of output timing signals with independent timing and polarity inversion
- Automatic detection and generation of horizontal and vertical video timing signals
- Support for multiple combinations of blanking or synchronization signals
- Automatic detection of input video control signal polarities
- Programmable output video signal polarities
- Generation of up to 16 additional independent output frame synchronization signals
- High number of interrupts and status registers for easy system control and integration
- N/A
- (Xilinx Answer 32913) Why do some Max Lines Per Frame values cause a "XST failed for v_timebase_v1_0." error during generation?
- (Xilinx Answer 39413) What signals are needed for the timing to be correctly detected and regenerated?
Applies To
IP
- Video Timing Controller