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AR# 32755

Virtex-6 Embedded Tri-mode Ethernet MAC Wrapper v1.2 - Release Notes and Known Issues for ISE 11.2

Description

Keywords: Virtex-6, TEMAC, tri-speed, patch, installation, instruction, ip2_L, IP Update 2, LXT, SXT

This Answer Record contains the Release Notes for the Virtex-6 LogiCORE Embedded Tri-mode Ethernet MAC Wrapper v1.2 which was released in ISE 11.2 and includes the following:

-General Information
- New Features
- Bug Fixes
- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Solution

General Information

- Supports automatic generation of HDL wrapper files for the Virtex-6 Tri-Mode Ethernet MAC
- Instantiates user-configurable Ethernet MAC physical interfaces (GMII, MII, RGMII, SGMII and 1000Base-X PCS/PMA configurations are supported)
- Provides a FIFO-based example design
- Provides a demonstration testbench for the selected configuration

Known Issues

- Virtex-6 solutions are pending hardware validation.

- Software Support for the Virtex-6 Lower Power parts was added in this release, but the Tri-Mode Ethernet Mac Wrapper does not yet support these devices and cannot be generated from CORE Generator targeting Virtex-6 Lower Power. Pending further testing, support for Virtex-6 Lower Power parts is planned for 11.3. To work around this issue, you can set your project to target an equivalent Virtex-6 LXT device which will allow you to generate the IP.

(Xilinx Answer 33043) Virtex-6 Embedded Tri-mode Ethernet MAC Wrapper v1.2 - "Error Place:1153 - A clock IOB / BUFGCTRL pair not placed at optimal site"



AR# 32755
Date Created 06/05/2009
Last Updated 06/25/2009
Status Active
Type General Article