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AR# 32756

11.4 Timing Analyzer/Trce, Virtex-5 - Extra paths analyzed with respect to block RAM (additional delays through address pins of block RAM)

Description

When I run timing analysis, the number of paths increase and they are associated with my block RAM. Why?

Solution

Trce/Timing Analyzer are missing the worst-case timing paths through address pins of block RAM components in ISE design tools 10.x and older.

This change occurs in 11.2. This issue only affects block RAM elements. Timing paths were missing to the address pins of the block RAM. The timing analysis would analyze some, but not all the correct address pins of the block RAM. It would analyze an odd number of the address pins, but not all or the correct ones. Now, all the address pins are analyzed, regardless of the DATA_WIDTH setting. The Timing Analyzer tools analyze the address pins correctly if a signal is driving them. The timing report from the analysis in 11.2, or the patched version of 10.1.03/11.1, has an increase in the number of items or paths analyzed. This increase in the timing report is expected. Once 11.2 or the patch is installed, you will need to re-implement the design to insure you meet timing on these new timing paths.

AR# 32756
Date Created 05/22/2009
Last Updated 02/16/2010
Status Active
Type Release Notes
Tools
  • ISE Design Suite - 10.1
  • ISE Design Suite - 10.1 sp1
  • ISE Design Suite - 10.1 sp2
  • More
  • ISE Design Suite - 10.1 sp3
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
  • Less