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AR# 32771

Distributed Memory Generator v4.1 Rev1 - Release Notes and Known Issues for ISE 11.2


This Release Notes and Known Issues Answer Record is for the Distributed Memory Generator v4.1 Rev1 Core, released in ISE 11.2, and contains the following information: 


- General Information 

- New Features 

- Bug Fixes 

- Known Issues 


For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:  



General Information 


The Xilinx Distributed Memory Generator v4.1 Rev1 LogiCORE should be used in all new designs for supported families wherever a distributed memory is required. This core supersedes all versions of the previously released Distributed Memory LogiCORE.  


New Features in v4.1Rev1 


- ISE 11.2 software support 


- Virtex-6 and Spartan-6 device support 



Bugs Fixed in v4.1 Rev1 


- Incorrect address bus and select lines in Figures 4 and 6 in the Distributed Memory Generator data sheet 

- CR # 511558 



Known Issues in v4.1 Rev1 


- Virtex-6 and Spartan-6 solutions are pending hardware validation 


(Xilinx Answer 21393) - When a large Distributed Memory Generator IP is generated, CORE Generator runs out of memory and fails to generate - CR 431917 


(Xilinx Answer 32753) - Default Data option is unavailable in the core GUI for Spartan-6 devices - CR 522888 


(Xilinx Answer 32816) - VHDL behavioural model drives unknown value on DOUT for Spartan-6 devices - CR 523629 



Revision History 

06/24/2009 - Initial Release

AR# 32771
Date Created 06/10/2009
Last Updated 05/23/2014
Status Archive
Type General Article