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11.2 & 11.1 EDK, xps_mailbox_v1_00_a - Mailbox core fails in timing when 2 PLBv46 buses are running at different clock speeds

AR# 32803

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Topic EDK-IP-Other
Last Updated 06/22/2009
Status Active
Description

Keywords: plbv46, mailbo, mailbox

There is an error in the TCL code that generates timing constraints for the mailbox. However, it looks like there is a problem with synthesis (XST) causing a timing error.

Solution

This issue has been fixed in the latest xps_mailbox, and is available in EDK 11.3.

EDK 11.3 is available at:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
 
 
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