My data does not appear downsampled when I use "first value of frame" with a latency of 0 with the downsample block. Why?
When the downsample block is used with the option 'First value of frame' with a latency of 0, the design creates a combinatorial path between the two clock domains as the downsample circuit itself contains no register.
As a result, the signal on the output of the downsample block in question is still at the rate of the original domain until it is registered in the new domain. If this signal is driven to Simulink blocks (not Xilinx Blockset blocks), they will still be sampled at the higher rate.
Using the block in this nature is poor design practice because it can produce unpredictable results. The output of this block should be immediately driven into a System Generator block which registers the signal in the new domain.