UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 32833

Modelsim/Questasim - Fatal: (vsim-3471) Slice range (35 downto 32) does not belong to the prefix index range (31 downto 0)

Description

The following error prevents me from running simulation:

# ** Fatal: (vsim-3471) Slice range (35 downto 32) does not belong to the prefix index range (31 downto 0).

# Time: 0 ns Iteration: 0 Process: /block_level_tb/cpri_wrapper_top_master/cpri_reuse_inst_inst_cpri_jb_inst_wrapper_jb_ram_inst_jb_ram_mram_jb_ram/
ramb18sdp_inst/safe_mode/prcs_clk File: C:/Xilinx/10.1/ISE/vhdl/src/unisims/unisim_VITAL.vhd

# Fatal error in Process prcs_clk at C:/Xilinx/10.1/ISE/vhdl/src/unisims/unisim_VITAL.vhd line 152747

What does the error come from and how can I resolve it?

Solution

The error is possibly caused by an undesired width of initial value assigned to the RAM component in the code either by inference or instantiation.

For example, if RAMB36 is instantiated, it is expected to have any 36-bit value for INIT_A and INIT_B in order that output of each port (DO & DOP) can obtain appropriate initial value bits. If the value you specified is less than 36-bit, you can encounter this error in simulation.

The error can also occur if using the Simple Dual Port RAM macro (BRAM_SDP_MACRO) with different read and write port widths which is not supported.

Please refer to the libraries guide or user guide for allowed values of INIT attribute.

AR# 32833
Date Created 01/22/2010
Last Updated 01/22/2010
Status Active
Type General Article