We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 32842

12.3 PlanAhead- DRC errors when importing ports from HDL


I import I/O ports into PlanAhead tool using File > import IO ports > From HDL. After I have imported the .ucf into planAhead, a DRC check is done.

DRC check gives several fatal errors as below

DRC error - Terminal is single ended but has an IO std of LVDS_25 which can only support differential

I do have correct buffers instantiated in the HDL, so why is this happening?


This is a known limitation in PlanAhead software. When you import the ports using HDL, PlanAhead tool does not parse the rest of the HDL file to see if appropriate buffers were instantiated

Performing pin planning on a synthesized netlist gives the tools more context to perform DRC.
AR# 32842
Date Created 10/26/2010
Last Updated 12/15/2012
Status Active
Type General Article
  • PlanAhead - 11.1
  • PlanAhead - 11.2
  • PlanAhead - 12.1
  • More
  • PlanAhead - 12.2
  • PlanAhead - 12.3
  • Less