Spartan-6 FPGA Integrated Block Wrapper v1.1 for PCI Express - Clock-to-out delay required on cfg_interrupt_n for simulation
Description
There is an issue in the simulation model for the Spartan-6 FPGA Integrated Block for PCI Express which causes the simulation to hang if an interrupt is transmitted and there is no clock-to-out delay modeled on the cfg_interrupt_n pin.
Solution
A delay of 1ps or greater is required. A work-around is included in <component name>/source/<component name>.v. This file is generated as part of the files delivered by CORE Generator.
For other Spartan-6 FPGA Integrated Block Wrapper v1.1 for PCI Express Known Issues and Release Notes, see (Xilinx Answer 32743).
This issue is resolved in ISE 11.3 and Spartan-6 FPGA Integrated Block Wrapper v1.2.
Revision History
09/16/2009 - Added fix version.
06/24/2009 - Initial Release
Applies To
IP
- Spartan-6 FPGA Integrated Endpoint Block for PCI Express