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AR# 32867 Spartan-6 FPGA Integrated Block Wrapper v1.1 for PCI Express - Designs which use the cfg_pm_wake_n input to generate a PME event should implement a timeout counter

Description

If a PME message is not acknowledged by the host within 100 ms (+50%/-5%) of clearing the PME Status bit, the Endpoint is required to re-transmit. This functionality is not provided by the Spartan-6 FPGA Integrated Block for PCI Express.

Solution

The user design must implement the timeout counter and re-transmit logic in fabric. This process will be documented in the ISE Design Suite 11.3 User Guide.

For other Spartan-6 FPGA Integrated Block Wrapper v1.1 for PCI Express Known Issues and Release Notes, see (Xilinx Answer 32743).

This issue is resolved in ISE 11.3 software and Spartan-6 FPGA Integrated Block Wrapper v1.2.

Revision History
09/16/2009 - Added fix version.
06/24/2009 - Initial Release

Actions

AR# 32867
Date Created 06/09/2009
Last Updated 04/20/2012
Status Active
Type
IP
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )
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