UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 32867

Spartan-6 FPGA Integrated Block Wrapper v1.1 for PCI Express - Designs which use the cfg_pm_wake_n input to generate a PME event should implement a timeout counter

Description

If a PME message is not acknowledged by the host within 100 ms (+50%/-5%) of clearing the PME Status bit, the Endpoint is required to re-transmit. This functionality is not provided by the Spartan-6 FPGA Integrated Block for PCI Express.

Solution

The user design must implement the timeout counter and re-transmit logic in fabric. This process will be documented in the ISE Design Suite 11.3 User Guide.

For other Spartan-6 FPGA Integrated Block Wrapper v1.1 for PCI Express Known Issues and Release Notes, see (Xilinx Answer 32743).

This issue is resolved in ISE 11.3 software and Spartan-6 FPGA Integrated Block Wrapper v1.2.

Revision History
09/16/2009 - Added fix version.
06/24/2009 - Initial Release
AR# 32867
Date Created 06/09/2009
Last Updated 08/26/2013
Status Active
Type General Article
IP
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )