MIG v3.1, Virtex-6 - Enabling KEEP_HIERARCHY option in synthesis causes ERROR:PhysDesignRules:368 during BitGen

AR#	32868	Search For Another Answer
Topic	MIG
Last Updated	06/14/2011
Status	Active

Description

When the KEEP_HIERARCHY option is enabled in XST, the following errors occur in BitGen: 

"ERROR:PhysDesignRules:368 - The signal  
</gen_v6_ddr3_phy.phy_top0/u_phy_clock_io/u_ phy_ck_iob_fb/u_iobuf_ck/split_buf_net> is incomplete. The signal is not  
driven by any source pin in the design." 

"ERROR:PhysDesignRules:368 - The signal </gen_v6_ddr3_phy.phy_top0/u_phy_data_io/gen_dqs[0].u_phy_dqs_iob/gen_iobuf_ddr2.u_iobuf_dqs/split_buf_net> is incomplete. The signal is not driven by any source pin in the design."

Solution

By default, the implementation batch file provided with MIG designs (ise_flow.bat) does not enable the KEEP_HIERARCHY setting in XST. However, if this is enabled by the user, these BitGen errors occur.  

To work around this issue, either disable the KEEP_HIERARCHY setting or set the following environment variable:  

XIL_MAP_NO_PARTIAL_FLATTENING