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AR# 32868

MIG v3.1, Virtex-6 - Enabling KEEP_HIERARCHY option in synthesis causes ERROR:PhysDesignRules:368 during BitGen

Description

When the KEEP_HIERARCHY option is enabled in XST, the following errors occur in BitGen: 

ERROR:PhysDesignRules:368 - The signal  
</gen_v6_ddr3_phy.phy_top0/u_phy_clock_io/u_ phy_ck_iob_fb/u_iobuf_ck/split_buf_net> is incomplete. The signal is not  
driven by any source pin in the design.


ERROR:PhysDesignRules:368 - The signal </gen_v6_ddr3_phy.phy_top0/u_phy_data_io/gen_dqs[0].u_phy_dqs_iob/gen_iobuf_ddr2.u_iobuf_dqs/split_buf_net> is incomplete. The signal is not driven by any source pin in the design.

Solution

By default, the implementation batch file provided with MIG designs (ise_flow.bat) does not enable the KEEP_HIERARCHY setting in XST.

However, if this is enabled by the user, these BitGen errors occur.  

To work around this issue, either disable the KEEP_HIERARCHY setting or set the following environment variable:  

XIL_MAP_NO_PARTIAL_FLATTENING

AR# 32868
Date Created 06/09/2009
Last Updated 10/15/2014
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • MIG