The Virtex-6 QDRII+ SRAM design requires that the Data Read group follow these bank selection rules:
1. Data Read groups must be selected in banks that are within +/- 1 bank vertically of the Address/Control group, which is located next to an MMCM.
2. Data Read groups must be selected in consecutive banks in a given column following the above rule. Skipping banks is not allowed in the case of Multiple Data Read banks.
Currently, MIG does not apply the above two rules for the Data Read group selection.
If the second rule is not followed, the following error messages display in the MRP report file:
ERROR: Place:906 - Components driven by IO clock net <u_user_top/u_phy_top/clk_cq<1>> can't be placed and routed because location constraints are causing the clock region rules to be violated. IO Clock net <u_user_top/u_phy_top/clkcq<1>> is being driven by BUFIO <U_user_top/u_phy_top/u_phy_iob/nd_io_inst.u_phy_read_cq_io/qdr_cq_bufio_inst> locked to site "BUFIODQS_X2Y6" Because of this location constraint, <u_user_top/u_phy_top/clk_cq<1>> can only drive clock regions "CLOCKREGION_X1Y7, CLOCKREGION_X1Y6, CLOCKREGION_X1Y5". The following components driven by <u_user_top/u_phy_top/clk_cq<1>> have been locked to sites outside of these clock regions:
u_user_top/u_phy_top/u_phy_iob/nd_io_inst.u_phy_data_io/d_q_mem_inst.d_q_inst/IO_Q_D.u_iserdes_q (Locked Site: ILOGIC_X2Y74 CLOCKREGION_X1Y1)
These errors are accurate, so different banks must be selected.