MIG v3.1, Virtex-5 DDR2 SDRAM - TWR violations occur at low frequencies

AR#	32871	Search For Another Answer
Topic	MIG
Last Updated	06/14/2011
Status	Active

Description

When the Virtex-5 DDR2 design is simulated at low frequencies, there is a tWR violation when the sequence of commands is WRITE -> ACTIVATE -> PRECHARGE.

Solution

This occurs when the timing counter of WRITE -> ACTIVATE is less than the timing counter of ACTIVATE -> PRECHARGE (TRAS_COUNT). Consequently, the PRECHARGE command is issued before the current write burst ends.  

The issue is with the counter "precharge_ok_cnt_r" in the DDR2_CTRL module. Before the counter is loaded, there should be a check on the current count value.  

To work around this issue, the following is the suggested fix for VHDL code (ddr2_ctrl): 

Existing Code  


elsif (state_r = CTRL_ACTIVE) then 

precharge_ok_cnt_r <= TO_UNSIGNED(TRAS_COUNT,5); 

elsif (precharge_ok_cnt_r /= "00000") then 

Modified Code


elsif (state_r = CTRL_ACTIVE) then 

if (precharge_ok_cnt_r <= TO_UNSIGNED(TRAS_COUNT,5)) then 

precharge_ok_cnt_r <= TO_UNSIGNED(TRAS_COUNT,5); 

else 

precharge_ok_cnt_r <= precharge_ok_cnt_r - 1; 

end if; 

elsif (precharge_ok_cnt_r /= "00000") then 

This issue is resolved in MIG 3.2.