Virtex-6 FPGA Integrated Block Wrapper v1.3 for PCI Express - Use of the trn_rnp_ok_n signal not supported for the 8-lane Gen 2 Integrated Block Mode
Description
Known Issue: v1.3, v1.2
Use of the trn_rnp_ok_n signal is not supported in the 8-lane Gen 2 Integrated Block mode.
Solution
Users must accept packets in the order presented by the block, and cannot use trn_rnp_ok_n to stall only Non-Posted packets. Using trn_rdst_rdy_n to stall all packets is allowed. This issue is being investigated and a resolution to this problem is scheduled for an upcoming release.
For other Virtex-6 FPGA Integrated Block Wrapper v1.3 for PCI Express Known Issues and Release Notes, see (Xilinx Answer 33276).
Revision History
09/16/2009 - Updated for ISE Design Suite 11.3 and wrapper v1.3
06/24/2009 - Initial Release
Applies To
IP
- Virtex-6 FPGA Integrated Endpoint Block for PCI Express