UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 32915

Virtex-6 FPGA Integrated Block Wrapper v1.3 for PCI Express - Use of the trn_rnp_ok_n signal not supported for the 8-lane Gen 2 Integrated Block Mode

Description


Known Issue: v1.3, v1.2



Use of the trn_rnp_ok_n signal is not supported in the 8-lane Gen 2 Integrated Block mode.

Solution


Users must accept packets in the order presented by the block, and cannot use trn_rnp_ok_n to stall only Non-Posted packets. Using trn_rdst_rdy_n to stall all packets is allowed. This issue is being investigated and a resolution to this problem is scheduled for an upcoming release.



For other Virtex-6 FPGA Integrated Block Wrapper v1.3 for PCI Express Known Issues and Release Notes, see (Xilinx Answer 33276).



Revision History

09/16/2009 - Updated for ISE Design Suite 11.3 and wrapper v1.3

06/24/2009 - Initial Release
AR# 32915
Date Created 06/10/2009
Last Updated 08/06/2010
Status Active
Type ??????
IP
  • Virtex-6 FPGA Integrated Endpoint Block for PCI Express