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AR# 32916

SPI-4.2 v9.2 - Virtex-6 Verilog timing simulation does not work with SDFMAX

Description

For Dynamic Alignment core configurations, Verilog timing simulation does not work with SDFMAX. This might result in data corruption on the Sink core user interface signal SnkFFDat.

Solution

This is a known issue with the Netgen tool that creates the SDFMAX timing data. 

 

To work around this issue, use SDFMIN instead of SDFMAX in Verilog timing simulation. This work-around is already implemented in the Example Design timing simulation scripts for MTI and NCSIM but not for VCS simulator. 

 

Revision History 

06/24/2009 - Initial Release

AR# 32916
Date Created 06/10/2009
Last Updated 05/23/2014
Status Archive
Type General Article