^

AR# 32920 SPI-4.2 Lite v5.1 - Virtex-6 design might fail timing in PAR

In some cases, the following timing constraint might fail in PAR:
TS_RDClk_P = PERIOD TIMEGRP "RDClk_P" 225 MHz HIGH 50% INPUT_JITTER 0.2 ns

To work around this issue, make the following changes in the UCF file:

1. Comment out the following constraint:

# NET "<snk_core_instant_name>/U0/pl4_lite_snk_reset0/rdclk0_rst_gen/reset_out_i*" MAXDELAY = 2.38 ns;

2. Add the following constraints in the UCF file:

INST "<snk_core_instant_name>/U0/pl4_lite_snk_reset0/rdclk0_rst_gen/reset_out*" TNM = snk_rdclk_reset;
INST "<snk_core_instant_name>/U0/pl4_lite_snk_io0/virtex*/*IDDR" TNM = snk_iddr;
TIMESPEC "TS_Snk_reset_iddr" = FROM "snk_rdclk_reset" TO "snk_iddr" "TS_RDClk_P"/ 4 DATAPATHONLY;
TIMESPEC "TS_Snk_reset_ffs" = FROM "snk_rdclk_reset" TO "FFS" "TS_RDClk_P";

Essentially, the commented MAXELAY contraint is replaced with two constraints: the non-critical reset timing path (TS_Snk_reset_iddr) and the critical reset timing path (TS_Snk_reset_ffs).

This issue has been fixed in v5.2 of the Core, available in ISE 12.1

Revision History

06/24/2009 - Initial Release

AR# 32920
Date Created 06/10/2009
Last Updated 12/15/2012
Status Active
Type General Article
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