Virtex-6 Integrated Block Wrapper v1.2 for PCI Express - When I implement an x8 Gen 2 mode design that uses an MPS capability of 512 bytes, this causes timing failures on the integrated block's BRAM interface
Description
Known Issue: v1.2
When I implement an x8 Gen 2 mode design that uses an MPS capability of 512 bytes, this causes timing failures on the integrated block's BRAM interface.
Solution
This issue only affects implementation and timing closure; you can still simulate 512 byte MPS.
Constraints will be added to the UCF file in 11.3 to help in timing closure.
For other Virtex-6 Integrated Block Wrapper v1.2 for PCI Express Known Issues and Release Notes, see (Xilinx Answer 32742).
Revision History
06/24/2009 - Initial Release
Applies To
IP
- Virtex-6 FPGA Integrated Endpoint Block for PCI Express