UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 32925

MIG v3.1, Virtex-6 QDRII+ - Issues exist in calibration logic that require an updated phy_read_stage1_cal.v module

Description

There are numerous fixes to the MIG 3.1 QDRII+ Virtex-6 calibration logic that were released in MIG 3.2. In particular, issues were seen during simulation with a Cypress memory model. However, updating the calibration module is recommended for all users.

Solution

Please download the udpated phy_read_stage1_cal.v module from the following location and replace with the file in the generated MIG design: 

http://www.xilinx.com/txpatches/pub/applications/misc/ar32925.zip

These calibration issues were resolved in MIG 3.2.

AR# 32925
Date Created 06/10/2009
Last Updated 05/21/2014
Status Archive
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • MIG