AR #32927 - 11.x XST - What is new in XST for Virtex-6 and Spartan-6 devices?

AR#	32927
Part	SW-XST
Last Modified	2009-07-08 00:00:00.0
Status	Active
Keywords	error, warning, different, behavior, new, Spartan-6, Virtex-6, XST, parser, naming convention, upgrade, design, port, 11.2, what's, 11.x

Solution

In 11.2, XST introduced a new VHDL/Verilog parser for Virtex-6 and Spartan-6 families.

The new parser brings a lot of improvements to XILINX synthesis solution.
- Significantly enlarges VHDL/Verilog language coverage, including a great support for complex data structures such as records, multi-dimensional arrays, array of records, etc.
- Allows greater flexibility in design coding.
- Significantly reduces runtime and memory usage for processing of various HDL constructs.
- Processing of complex if, then, else, and case statements.
- Functions and generics calculation.
- Structural designs processing.

However, several constructs supported in the XST Standard version for older FPGA families (such as Virtex-5 and Spartan-3) are not VHDL/Verilog LRM compliant. Some of them are rejected by the new parser and some of them are interpreted differently. Such situations will require some VHDL/Verilog code changes to successfully process the design using the new parser.

In addition, several naming conventions were improved in XST for Virtex-6 and Spartan-6 families. The names are more clear and predictable. However, these changes might have an impact on existing UCF files and require some modification.

The goal of this solution record is to provide the list of changes in XST for Virtex-6 and Spartan-6 devices compared to XST Standard, which will require some designs adaptation when migrating designs to Virtex-6 and Spartan-6.


1) List of HDL constructs that need to be reworked before re-targeting the code for Virtex-6 and Spartan-6 devices.

Topic ...............................................................................Message in XST for...........................................AR Number.........................
.................................................................................Virtex-6 and Spartan-6 Devices...........................................................................
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Signal and Component Have the Same Name....................HDLCompiler:40........................................ (Xilinx Answer 32971)
in a Scope
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Library and Component Have the Same Name...................HDLCompiler:40........................................(Xilinx Answer 32993)
in a Scope
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Instance and Component Have the Same Name.................HDLCompiler:40........................................ (Xilinx Answer 32997)
in a Scope
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Signal and Process Label Have the Same Name................HDLCompiler:56......................................... (Xilinx Answer 32998)
in a Scope
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translate_off and translate_on Directives with...................HDLCompiler:940...................................... (Xilinx Answer 32974)
Different Keywords
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Size Mismatch in Assignment..............................................HDLCompiler:410...................................... (Xilinx Answer 32975)
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Direct instantiation without Using Expanded Name..............HDLCompiler:69....................................... (Xilinx Answer 32976)
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Multi-Source in FSM Description..........................................HDLCompiler:637...................................... (Xilinx Answer 32979)
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Constant Declaration Depends on the Signal......................HDLCompiler:545...................................... (Xilinx Answer 32980)
Initialized with another Constant
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Entity and Component Ports have Different Types.............HDLCompiler:377...................................... (Xilinx Answer 32981)
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Support of the ?last_value Predefined Attribute..................HDLCompiler:236...................................... (Xilinx Answer 32982)
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Multiple Declarations via Multiple use Clauses....................HDLCompiler:607...................................... (Xilinx Answer 32983)
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Constant Declared and Used in the Procedure...................HDLCompiler:16....................................... (Xilinx Answer 32984)
Interface List
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Generic/Parameter Values Redefined................................HDLCompiler:852.......................................(Xilinx Answer 33031)
in Command Line
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2) HDL Constructs: Interpretation changes


Topic ..................................................................................Message in XST for...........................................AR Number...................
..................................................................................Virtex-6 and Spartan-6 devices........................................................................
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Dont Care Values.................................................................No Warning/Error........................................ (Xilinx Answer 33034)

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Compare Operation with Operands Having.........................Xst:647.........................................................(Xilinx Answer 33037)
Different Sizes

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Default Value of a Non-Initialized Signal..............................HDLCompiler:871..........................................(Xilinx Answer 32985)
of Type Integer or Float

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Location of Synthesis Metacomments.................................HDLCompiler:924..........................................(Xilinx Answer 33038)
in Verilog Files

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Elaborate command and Check Syntax Process..................No Warning/Error.........................................(Xilinx Answer 32986)

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3) New Naming Conventions


The changes in naming conventions are highlighted in this table